First in first out is an approach for supervising database work demands from queues or stacks in computer programming in a way that the very initial demand is handled first. In a computer hardware, an arrangement of flip-flops acts as read/write memory to store information coming from individual clock domain and forwarding the same to diverse clock domain when requested ensuing a first in first out format. The feeder clock domain provisioning information to FIFO is frequently stated as input clock or the write logic and the one extracting that information is frequently stated as output clock or read logic. The FIFO approach is mainly designed to achieve a safe and secure pass or exchange of a single to large bit of information either in an environment under the control of same clock, handling two different ends of a sender and a receiver or in an environment handling exchange between two distinct clock controls. Now, FIFOs can be synchronous or non-synchronous based on the commanding clock either it been same for both sender and receiver or it been two distinct values for sender and receiver, correspondingly. There is if a single clock control signal for write and read operations then the FIFO managing the data is synchronous or if there are two different clock control signals for read and write operation, then at that juncture existent FIFO might be non-synchronous or simply asynchronous natured. The flag signs every so often termed in FIFO indicating full and empty conditions are to be considered prudently which implied that no more data may perhaps be written or pushed in FIFO when its full and no data could be read when its empty, so as to prevent losing essential data or generating irrelevant data. The binary counters are used as pointers to control the generation of full and empty conditions in designing synchronous FIFO and likewise gray counters are used as pointers in asynchronous FIFO designing.
These are the FIFO designs where data values are written and read sequentially into an group and stored in memory array with the help of a clock signal common for both the writer and reader modules; one module writes data sequentially into the FIFO array and the other module sequentially reads, retrieving the same data values, maintaining the secure transmission throughout. As there is no clock domain crossing involved, there is straight onward generation of raised full and empty flags indicating the status of data values in FIFO, eventually the programmers can create the partially fully and partially empty condition flags, and this technique is proven useful in many applications.
Exchange of data values securely between the two different modules running at the control of two discrete clocks is achieved in asynchronous FIFOs, which can be used as memory buffers. The data values are written into the FIFO by the sender module controlled by one clock frequency and the same are read out by the receiver module controlled by another clock frequency; successful run of these type of buffers are installed with two ports one for the input (pushing the values in) and the other for the output (popping the values out). Mostly, the FIFOs are the environments where the writing module runs faster than the reading module, though the average speed of transmission of data remains continuous with the different values of speed and data accessing points. The job of the pointers in FIFO need to maintain the tabs on the number of memory locations in FIFO which are yet touched to read and write and the respective control logic unit to avoid the data loss due to overflowing and under flowing. The task while designing FIFO structures is that it should inherit the ability to synchronize itself according to the pointer logic of different clock and control the securing of locations of read and write operations. The FIFO pointer logic and the synchroniser circuit needs to be analysed in detail to comprehend synchronization among both pointer logics of the two ends of FIFO thereby allowing access to read and write ports of FIFO running in the impression of distinct clocks.
1.2 Motivation of the thesis
Constructive potentials of FIFOs and asynchronous FIFO design:
‘ With the advantageous feature of FIFOs, in most of the System-on-Chip designs (SoCs) it is possible made to securely transmit data between the two chronologically discrete domains which are non-synchronous to each other, as there are often cases in SoCs where components mounted operate with different clocks.
‘ FIFOs are needful even when there are situations where sender and receiver modules running under the impression of same clock signal and eventually both their throughputs can be coordinated. There are evident cases when supply rate of data inputs from sender cannot be endured by the receiver or when the receiver requesting a faster rate of data inputs which the sender cannot endure; so as to mend this fissure between the capacities of sender & receiver we require a synchronous FIFO to tolerate the supply & consumption of data and act as an elastic supple buffer.
The FIFOs working asynchronously are used as memory buffers located between two asynchronous clock frequencies to exchange data securely. Data is written by transmitting block into the FIFO starting from one initial clock domain and the same is read from the other domain of another clock of the receiver block. This requires a memory design wherein a memory equipped with two ports is accessible- one is for input (to write data or push data) operation and the other is for output (to read or pop) operation. Commonly FIFOs are used wherever the write operation is usually more rapid than read operation. Conversely, even with the diverse categories of speed and access, the normal average rate of transferring data remains constant. FIFO pointers retain trail of number of location sites in FIFO memory, read and written and the equivalent control logic circuit avoids from under flowing or overflowing of FIFO. FIFO architectures integrally have a contest of synchronizing itself in accordance with the pointer logic accepted by other clock domain and safely control the operations of read and write running in the FIFO packing locations. An ample and thoughtful study of operating a synchronizer circuit alongside with the operation of pointer logic is essential to realize and recognize the synchronization of two pointer logics of FIFO circuits; it is accountable for accessing the two ports of FIFO circuit i.e. the read and write ports individually controlled by dissimilar clocks .
Asynchronous circuits preserve the assumption that signals can attain two values of 0 and 1 i.e. they are binary in form, but eliminate the theory of time being discrete. These asynchronously running circuits are equipped with several possible beneficial features :
Zero clock skew- Clock skew can be implied as variance in the arrival times of the signal from clock, at diverse portions of the circuit. Since asynchronous circuits by characterization have no globally distributed clock, there is no necessity to concern about clock skew. Synchronous systems in incongruence to non-synchronous systems, tries to accommodate the skew and frequently slow down their circuits. As there is a decline in feature sizes, clock skew becomes a much bigger concern.
Lesser power consumption- Usual synchronous circuits need to toggle the clock lines, and perhaps pre-charge the signals and discharge them too, present in sections of an unemployed circuit in the recent computation. For an illustration, even though a floating point entity might not be used on a processor, in any given instruction stream, the unit must still be operated by the clock. Even though asynchronous circuits frequently involve additional transitions on the computation route than synchronous circuits, they mostly have transitions only in ranges involved in the current computation.
Average-case as an alternative of worst-case performance- Synchronous circuits need to pause until all probable computations have concluded earlier before latching the results, ending up in yielding worst performance in that case. Several asynchronous systems can sense exactly when a computation or a calculation has finalised on completion, authorising them to reveal a case with average performance.
Ease in global timing issues- In structures like as in a synchronous system microprocessor, the clock used in that system, and its performance, is controlled by the slowest critical path. Hence, most regions or sections of a circuit must be reasonably optimized and improved to accomplish the highest clock rate, including less or rarely used sections of the system. Meanwhile various asynchronous systems work at the speed of the presently operating circuit path; barely used regions of the circuit in the system can be left without being optimized without affecting system performance severely.
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