The ARM processor is a Reduced Instruction Set Computer (RISC), a type of microprocessor that recognizes a relatively limited number of instructions. ARM cores are very simple which means that they are manufactured using a comparatively small number of transistors, which makes them cheaper to design and produce. One advantage of RISC processors is that they can execute instructions very quick because the instructions are so simple. This architecture is different from most major microprocessors such as the Itanium processors and SPARC as it is mainly designed for embedded systems. ARM processors are generally processors that implement the ARM architecture specifications.
The ARM engineering is one of the quickest developing microcontroller designs in implanted gadgets. It gives two distinctive software engineer’s models 32-and 16-bit.Because ARM licenses the architecture instead of manufacturing chips. the ARM architecture is highly modular: the only mandatory component the integer pipeline. thus making it highly efficient.
ARM Instruction Set
All instruction are 32 bits long.
Most instructions can be conditionally executed
Load/store instruction set- no direct manipulation of memory Contex
Example : (1) SUB r0,r1, #5
(2) ADD r2,r3,r3, LSL #2
R2=r3+(r3 * 4)
(3) ANDS r2,r2, #0x25
R2=r2 & 0x25
ARM Thumb Instruction Set
The functionality of the Thumb instruction set is a subset of the functionality of the 32-bit ARM instruction set.ARM architecture versions v4T and above define a 16-bit instruction set called the Thumb instruction set. Example:
(1) ADD r1, #5
(2) AND r2 ,#0x25
R2=r2 & 0x25
Vector Floating Point (VEP) Instruction
VEP (Vector Floating Point) technology is an FPU(Floating Point Unit) coprocessor extension to the ARM architecture.
It provides low-cost single-precision and double-precision floating-point computation.
The VEP architecture was intended to support execution of short “ vector mode “ instructions but these operated on each vector element sequentially.
VEP provides floating-point computation suitable for a wide spectrum of applications such as PDAs, Voice compression, smart phones, and decompression, three-dimensional graphics and digital audio, printers and automotive applications.
Advanced SIMD (NEON)
NEON instruction are executed as a major aspect of the ARM or Thumb instruction stream. This improves programming advancement, debugging, and integration compared to using an external accelerator. Traditional ARM or Thumb instructions deal with all program flow and synchronization. The NEON instructions perform:
data copying between NEON and general purpose registers
data type conversion
Pipelining– an efficient technique to complete an average of one instruction every cycle.
ARM7 has a 3-stage pipeline.
ARM9 has a 5-stage pipeline.
ARM10 has 6 and ARM11 has 8, both with branch prediction to avoid pipeline stall due to branching.
ARM7 (3 Stages)
ARM9 (5 Stages)
ARM10 (6 Stages)
ARM11( 8 Stages)
This paper presents an overview of ARM architecture starting from different instruction Set and pipeline. Special emphasis is given to ARM extensions (SIMD and NEON) aimed for optimization of multimedia applications. Some problems are brought out to attention and could serve as a starting point for the future improvements of processor architecture and instruction sets aimed specifically for the multimedia applications.
ARM Limited licenses its cores and architectures to other companies which will either integrate the cores into their own products or manufacture a new chip based on the licensed architecture. ARM does not fabricate its own chips.
4. Steve Furber. ARM System-on-Chip Architecture. Addison-Wesley,
2nd edition, 2000.
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