Implementation Of Area, Power, Delay Efficient Carry-Select Adder
Dept. of Electronics & telecommunication
Dhole Patil college of engineering,
Prof. Kanchan Pujari
Dept. of Electronics & Telecommunication
Dhole Patil college of engineering,
Abstract— Carry Select Adder is one of the high speed adders used in many computational systems to perform fast arithmetic operations. In rapidly growing mobile industry the faster arithmetic unit, less area and low power arithmetic units are needed. Modified CSLA architecture has developed using Binary to Excess-1 converter. In the proposed architecture scheme, carry selection operation is scheduled before the calculation of final-sum, which is different from the conventional approach. Bit patterns of two carry words (corresponding to Cin = 0 and 1) and fixed Cin bits are used for logic optimization of Carry Select and generation units. Efficient CSLA design is obtained using optimized logic units. The recently proposed CSLA design involves significantly less delay and area than the recently proposed BEC-based CSLA. Due to the small carry-output delay, The newly design proposed CSLA design is a best candidate for square-root (SQRT) CSLA.
Keywords— Carry Select Adder, arithmetic unit, low-power design
Low power, high performance, and area efficient VLSI systems are increasingly used in mobile and portable devices, standard receivers, and some biomedical instrumentation. Adder is the main component of an arithmetic unit. A complex digital signal processing system involves many adders. An efficient adder design essentially improves the performance of a complex Digital Signal Processing system. Ripple carry adder (RCA) uses a simple design, but carry propagation delay is the main factor in this adder. Carry look-ahead and carry select (CS) methods have been suggested to reduce the CPD of adders. A conventional carry select adder is an Ripple Carry Adder- Ripple Carry Adder configuration that generates a pair of sum words and output carry bits corresponding the input-carry (Cin = 0 and 1) and selects one out of each pair for final-sum and output-carry . Conventional CSLA has less Carry Propagation Delay than an RCA, but the design is not attractive since it uses a dual Ripple Carry Adder. To avoid dual use of Ripple Carry Adder in CSLA design. Kim and Kim  used one Ripple Carry Adder and one add-one circuit instead of two Ripple carry adders where the add-one circuit is implemented using a multiplexer . He et al.  proposed a square-root (SQRT)-CSLA to implement large bit-width adders with less delay. In a Square-root CSLA, Carry select adders with increasing size are connected in a cascading structure. The main objective of design is to provide parallel path for carry propagation that helps to reduce overall adder delay. Ramkumar and Kittur  suggested a binary to Binary to Excess-1 Converter based CSLA. The Binary to Excess-1 Converter based Carry select adder involves less logic resources than the conventional Carry select adder, but it has marginally higher delay. Carry select adder based on common Boolean logic (CBL) is also proposed in  and . The Common Boolean logic-based CSLA of  involves significantly less logic resource than the conventional Carry select adder but it has longer Carry propagation delay, which is almost equal to that of the Ripple Carry Adder. To overcome this problem, a SQRT-CSLA based on Common Boolean Logic was proposed in . However, the Common Boolean Logic-based SQRTCSLA design of  requires more logic resource and delay than the BEC-based square-root carry select adder of . We observe that logic optimization depends on availability of some redundant operations in the formulation, whereas adder delay depends on data dependence. In the existing designs, logic is optimized without any consideration to the data dependence. we have proposed a logic formulation for the CSLA.
2. Proposed System
Fig 2.1 Proposed Carry Select Adder Design
The proposed Carry select adder is based on the logic formulation given in (2a)–(2g), and its structure is shown in Fig. 2.1. It consists of one Half Sum Generator unit, one Full Sum Generator unit, one Carry Generate unit, and one Carry Select unit. The Carry Generator unit is composed of CG0 and CG1 corresponding to input-carry ‘0’ and ‘1’. The HSG receives two operands (A and B) and generate half-sum word S0 and half-carry word C0 of width n bits each. Both CG0 and CG1 receive S0 and C0 from the Half Sum Generator unit and generate two n-bit full-carry words C01 and C11 corresponding to input-carry respectively 0 and 1. The logic diagram of the HSG unit is shown in Fig. 2.2
Fig 2.2 Gate level design of the Half Sum Generator
The logic circuits of CG0 and CG1 are optimized to take advantage of the fixed input-carry bits. The optimized designs of input carry 0 and 1 are shown in Fig. 2.3 and 2.4 respectively.
Fig 2.3 Gate-level optimized design of (CG0) for 0 input carry
Fig 2.4 Gate-level optimized design of (CG1) for input-carry = 1
The Carry Select unit selects one final carry word from the two carry words available at its input line using the control signal Cin. It selects C01 when Cin = 0; otherwise, it selects C11. The Carry Select unit can be implemented using an n-bit 2:l MUX. However, we find from the truth table of the Carry Select unit that carry words C01 and C11 follow a specific bit pattern. If C01(i) = ‘1’, then C11(i) = 1, This feature is used for logic optimization of the Carry Select unit. The optimized design of the Carry Select unit is shown in Fig. 2.5
Fig 2.5 Gate level Carry Select design
The final carry word c is obtained from the CS unit. The MSB of c sent to output as Cout, and (n − 1) LSBs are XOR with (n − 1) MSBs of half-sum (S0) in the FSG [shown in Fig. 2.6 to obtain (n − 1) MSBs of final-sum (s). The LSB of s0 is XOR with Cin to obtain the LSB of s.
Fig 2.6 Gate Level Design of Full Sum Generator
3. System Block diagram
Fig. 7 Proposed SQRT-CSLA for n = 16. All intermediate and output signals are labeled with delay
The proposed Carry Select Adder this adder is design using other sub block like CG0 (input carry 0),CG1(input carry 1),CS(carry select),FSG(final sum gate),HFG(half sum gate) .first design all the sub block using logic gates, then connect all the sub block properly And design Proposed Carry Select Adder. Using Carry Select Adder design 2bit Carry Select Adder,3 bit Carry Select Adder, 4bit Carry Select Adder, 5bit Carry Select Adder and also design one 2 bit Ripple carry adder. Connect all Carry Select Adder and ripple carry adder according to the take two input of n-bits . All output of Carry Select Adder connect according to diagram and generate final output .Firstly two input of n bit is given to Half Sum Gate unit and output of HSG is given to CG0 ,CG1 and Full Sum gate unit .the all Carry Select Adder connect each other but in first 2 bit of input is given to the ripple carry adder and remaining bit given to the Carry Select Adders and generate the final output. The multipath carry propagation feature of the carry select adder is fully exploited in the square-root carry select adder, which is composed of a chain of carry select adders. Carry select adders of increasing size are used in the square-root carry select adder (SQRT-CSLA) to extract the maximum concurrence in the carry propagation path. Using the square-root carry select adder (SQRT-CSLA) design, large-size adders are implemented with significantly less delay than a single-stage carry select adder of same size. However, CPD between the carry select adder stages of square-root carry select adder is critical for the overall adder delay. Due to early generation of output-carry , the proposed carry select adder design is more favorable than the existing carry select adder designs for area–delay efficient implementation of square-root carry select adder. A 16-bit square-root carry select adder (SQRT-CSLA) design using the proposed carry select adder where the 2-bit RCA, 2-bit CSLA, 3-bit CSLA, 4-bit CSLA, and 5-bit CSLA are used.
Sr No. Bit Delay(ns)
1 16 2.48
2 32 5.03
5 Simulation Results
Fig. 5.1 RTL Schematic of 16 Bit SORT CSLA
Fig. 5.2 Technology Schematic of 16 Bit SORT CSLA
Fig. 5.3 Addition of 16 bit adder
Fig. 5.4 RTL Schematic of 32 Bit SORT CSLA
Fig. 5.5 Technology Schematic of 32 Bit SORT CSLA
Fig. 5.6 Addition of 32 bit adder
A simple approach is proposed in this paper to reduce the area and power of Square root Carry select adder (SQRT CSLA) architecture. The reduced number of gates of this work offers the great advantage in the reduction of area and also the power. The modified carry select adder architecture is therefore, low area, low power, simple and efficient for VLSI hardware implementation. The proposed carry select adder design involves significantly less area and delay than the recently proposed Binary to Excess- I Converter based carry select adder. Due to the small carry output delay, The proposed CSLA design is a good candidate for the SQRT adder.
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