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Design of High gain Low power down conversion Mixer used for Wireless LAN applications.

Ananda M

Doctoral student at Visvesveraya Technological University, Karnataka, India and

Presently working as Assistant Professor in the department of Electronics and communication

PESIT- Bangalore South Campus, Bangalore, India

[email protected]

Dr. A B Kalpana

Department of Electronics and communication

Bangalore Institute of Technology

Bangalore, India

[email protected]

Abstract— This paper aims at design of high gain and low power down conversion mixer operates at 2.5GHz. The proposed mixer generate Intermediate frequency (IF) signal of 100MHz from 2.4GHz Radio Frequency (RF) and 2.3GHz Local oscillator (LO). The simulation result shows that the third order input intercept point (IIP3) of -35.8806 dBm and the power consumption of 6.501mW. A comparison is made and shows that proposed mixer design has low power consumption and good conversion gain and can be used for 2.4GHz wireless communication.

Index Terms—Gilbert mixer, down-conversion, RF, Voltage conversion gain.

I. INTRODUCTION

A radio frequency (RF) mixer is a passive or active that converts a signal from frequency to other. It can either modulate or demodulate a signal. It has three signal connections which are called ports. These three ports are the Radio Frequency (RF) input, the local oscillator (LO) input, and the Intermediate frequency (IF) output as in Fig1.1.

Fig 1. Mixer Block diagram.

   As depicted in Fig 1.1 the mixer takes RF input signal at frequency fRF and mixes it with LO input at a frequency fLO and produces an Intermediate frequency IF output signal that consists of the sum and difference frequencies, fRF  ± fLO. The user provides a bandpass filter that follows the mixer and

When the sum frequency is used as the IF, the mixer is called a up-converter, when the difference is used the mixer is called a down-converter. The former is used in transmit channel, the later in a receiver.

   The down-conversion mixer in RF receiver decides the overall performance of the receiver. Presently with the advent of new wireless receiver devices, the speed of wireless service has to be increased and therefore the frequency band of 2.4GHz is set free for Industry, Scientific and Medicine (ISM).

   The main objective of the paper is to design low power and high conversion gain down-conversion mixer in 180nm technology. To achieve this the following parameters are analyzed,

1. Voltage conversion gain,

                 G = (2/π) (gm Rload)                       (1)

2. 1 dB Compression point.

                          

3. Intermodulation performance.

II. DESIGN METHODOLOGY

The topologies used in the design of mixer is discussed as follows:

A. Double Balanced Mixer cell(Gilbert Cell)

The most popular active double balanced mixer topology in RFIC design is the Gilbert Cell mixer, the circuit of which is depicted in Fig 2.This type of mixer exploits symmetry to remove the unwanted RF and LO output signals from the IF by cancellation.

The RF signal is applied to M1 and M2 Transistor which forms the transconductance stage and converts the RF input voltage into a current. This current is commutated by the switching stage of transistor M3 - M4 and M5 - M6. It can be seen from the Fig.2 that each side of the IF output is connected with two transistor 1800 phased LO signals so that the LO leakage from two transistors cancel each other. The LO feedthrough from two transistor M3 will be cancelled from M5 and any feedthrough from transistor M6 will be cancelled from that from M4. Therefore, we will observe only the mixed products of RF and LO at the output [6].

Fig 2. Double balanced Gilbert cell.

B. Current Mirror circuit

An ideal current mirror is a two port circuit that accepts an input Iref and produce an output current Iout = Iref. Also an ideal current mirror will have zero input resistance. From another point of view, two identical MOS devices that have equal gate-source voltage and operate in saturation carry equal currents [1].

Fig 3. Basic current mirror

The structure consisting of M1 and M2 in Fig 3 is called “current mirror”. In the general case, the devices need not be identical. Neglecting channel-length modulation, we can write

  (2)

  (3)

                          (4)

The key property of this topology is that it allows precise copying of the current with no dependence on process and temperature. The ratio of Iout and Iref is given by the ratio of device dimensions, a quality that can be controlled with reasonable accuracy.

    

III. PROPOSED DOWN CONVERSION MIXER

This proposed mixer design figure 4 involves following parts: the current mirror stage, switch stage and load. Constant current source is used to bias the transistor. The RF stage is known as transconductance stage where it converts the voltage in to current and the differential inputs given to the RF stage and to switching stage. Load stage is called as transresistence where current converted in to voltage.

Fig 4. Block diagram of down conversion mixer

The proposed Mixer design mainly consists of current mirror and double balanced mixer. Current mirror is mainly used to biases the transistor and the current mirror transistor are M7, M8 and M9. Resistance R is used to block AC signal and it passes DC and its value depends on the bias voltage of current mirror. The schematic of the proposed down conversion mixer is as shown in figure 5.

IV. DESIGN PROCEDURE

Fig.5. Schematic of proposed down conversion mixer

Calculation of Aspect ratio (W/L) of proposed system Figure.5.

1) For 180nm technology the standard value for the threshold voltages is 0.5V-0.6V and the gate to source voltage is 0.6V- 0.8V.

In the current mirror circuit the transistor operate in saturation region therefore the drain current equation is given by,

Id = ½ µn Cox (W/L) (Vgs – Vth) 2                                 (5)

The output power can be calculated as

P = Vdd Id, let power be 8mW, then Id = 2.42mA              (6)

µnCox for nMOS transistor of RF stage and current mirror is given by 519µ.                                                                   (7)

Substituting values from (6) and (7) in (1) and find the value of W for L = 180nm

W = 207µm.

For current mirror and RF stage transistor the width is taken as approximately 200µm.

2) The current starts dividing at LO stage equally therefore current is given by 1.21mA and substitute in equation (5)

Therefore W = 103µm.

For LO stage transistor the width is taken as approximately 100µm

V. SIMULATION RESULTS AND PERFORMANCE ANALYSIS

The test bench for simulating the various parameters is shown in Fig.7. The design was simulated using TSMC 180nm RF CMOS process and results are validated on Cadence Virtuoso IC 613. The voltage conversion gain is the ratio of RMS voltages of IF and RF signals.

Fig 6.Schematic design of Differential input differential output down conversion mixer.

Fig.7. Test setup for proposed down conversion mixer

Power conversion gain is the ratio of the power delivered to the load and available RF input power. In this case mixer’s input impedance and load impedance are both equal to the source impedance and therefore, the power and voltage conversion gain are the same. In this paper RF and LO frequency is set to 2.4GHz and 2.3GHz respectively and RF and LO power is taken as -50dBm and 5dB respectively. Fig 8 shows the graph between voltage conversion gains and LO frequency using PXF analysis. The voltage conversion gains are 20dB, 19.97dB and 10.4705dB at LO power is 0dB, 5dB and 10dB respectively.

Fig.8 Voltage Conversion Gain versus the LO signal power

In small signal conditions output power increases linearly with increase in the input signal power, when circuits shift toward large signal operation this relation is no longer linear. The 1 dB compression point is the measure of this nonlinearity. This is power where the output of the fundamental crosses the line that represents the output power extrapolated from small signal condition minus 1dB. To calculate 1dB compression point and IIP3 large LO and one medium RF tone is applied and QPSS analysis is performed. Then second tone as a small tone close to the RF signal frequency is applied and QPAC analysis is performed. The power of the 2nd small signal RF tone is taken small enough that IM1 and IM3 are in the there asymptotic ranges. As shown in Fig.9, the 1 dB compression point of proposed system is -6.8703 and Fig 10. Shows the IIP3 of proposed down conversion mixer.

Fig.9 1dB compression point- IIP3

   Fig.10. 3rd Order Intercept Point using QPSS and QPAC.

The third-order intercept point is the input power level at which the first and third order harmonics have the same output power level. From the graph shown in Fig 10. The input referred IP3 point is approximately -35.8806dBm.

 At last, the power dissipation is calculated. After the simulation using transient analysis, we got the current value of 1.99mA. So the power dissipation is 6.51mW.

Fig.11. Envelop transient response of proposed mixer

VI.  PERFORMANCE COMPARISON  

 .

                  VI. CONCLUSION

The proposed down conversion mixer is designed at 180nm technology with power supply of 3.3V, RF frequency of 2.4GHz and LO frequency of 2.4GHz to achieve low power dissipation of 6.501mW, 1 dB compression point of 6.8703dBm and IIP3 of -35.8806dBm.

.

References

[1] Arif A. Siddiqi and Tad Kwasniewski, “2.4GHz RF down conversion mixers in standard CMOS technology, ISCAS 2009.

[2] Wah Ching Lee, Kim Fung Tsang, Yi Shen, Kwok Tai Chui, “ A Current Bleeding CMOS Mixer Featuring Lo Amplification Based on current-Reused Topology” The 2001 IEEE international Symposium on circuits and System, Vol.4 No.1, January 2013.

[3] D Selvathi M pown and s Manjula, “Design and analysis of UWB down conversion mixer with linearization techniques”, WSEAS Transactions on Circuits and Systems, Vol 13, 2014.

[4] Rajendra D Khanphade, Santosh B. Patil, “ A 2.4GHz Double balanced Differential Input Differential Output Low Power High gain Gilbert Cell Down Conversion Mixer in TSMC 180nm CMOS RF process,” IEEE sponsored 2nd International Conference of Electronics and Communication System, pp. 1187-1193, 2015

[5] H Ghayvat, L Bandil, S C Mukhopadhayay and R Gupta, “A 2.4Ghz CMOS gilbert mixer in 180nm technology”, Communication Systems and Network Technologies (CSNT), 2015 Fifth International Conference on, Gwalior, 2015, pp. 781-785.doi: 10.1109/CSNT.2015.171

[6] Payam Gh, Afshar, Mahrokh Maghsoodi, Reza E Atani and Mehregan Mahdevi, “ A 3.5 GHz Low Noise Figure Mixer with High Conversion Gain for Wimax Systems”, Volume 3, Issue 5, May 2013.

[7] Praveen kumar and Rekha Yadav, “ Comparative analysis of CMOS Mixers in 45nm VLSI Technology”, International Journal of Innovative Science, Engineering & Technology, VOL 1, Issue 4, June 2014.

[8] Manoj kumar Pandram, R C Gurjar, “ A low Power down conversion CMOS Gilbert Mixer for Wireless Communication”, International Journal of Engineering Research and Application Vol 4, July 2014.

[9] Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, Tata Mc Graw-Hill edition, pp136-138, 2002.

[10] Behzad Razavi- “RF Microelectronics”, Prentice hall Inc.  2nd Edition, 1998

[11] Thomas H Lee, “Design of CMOS Radio Frequency Integrated Circuits”, Cambridge University Press, 1998.

[12] Douglas A Pucknell and Kamran Eshraghian, “The Design of CMOS Radio Frequency Integrated Circuits”, New York Cambridge University Press.

[13] Adel S Sedra, Kenneth C Smith, “Microelectronics Circuits”, sixth  Edition, Oxford university Press, 2004

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