A

Project Report on

Design of Power Efficient Multiplier using Area Delay Power Efficient Carry Select Adder

Submitted in partial fulfilment of the requirement for the award of the degree of

MASTER OF TECHNOLOGY

IN

VLSI SYSTEM DESIGN

Submitted

By

HANITHA RAGHAVA D

14A31D5701

Under the esteemed guidance of

Mr. V. Prashanth, M.tech, (Ph.D)

Associate. Professor, Dept. of ECE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

PRAGATI ENGINEERING COLLEGE

(Approved by AICTE, New Delhi & affiliated to JNTU Kakinada)

#1-378, ADB Road, Surampalem, E.G. District, A.P-533437

Ph: (08852) 252233, 34, 35 Fax: (08852) 252232 www.pragati.ac.in

2014-2016

CERTIFICATE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

PRAGATI ENGINEERING COLLEGE

(Approved by AICTE, New Delhi & affiliated to JNTU Kakinada)

#1-378, ADB Road, Surampalem, E.G. District, A.P-533437

Ph: (08852) 252233, 34, 35 Fax: (08852) 252232 www.pragati.ac.in

This is to certify that Project Report entitled, “Design of Power Efficient Multiplier using Area Delay Power Efficient Carry Select Adder” that is being submitted by HANITHA RAGHAVA DHAVILESWARAPU of Regd.No:14A31D5701 in partial fulfillment for the award of M.Tech degree in VLSI System Design as a record of bonafide work carried out by him in the ECE Department during Academic period 2014 - 2016.

HEAD OF THE DEPARTMENT

Mr. V. Prasanth, M.tech,(Ph.D)

Associate Professor

E.C.E Department

PRAGATI ENGINEERING COLLEGE

SURAMPALEM

ACKNOWLEDGEMENT

I would like to express our profound gratitude towards Sri V. Prasanth, Associate Professor & Head of the Department, Electronics and Communication Engineering, who played a supervisory role to utmost perfection, enabled us to seek through my M. Tech project and for guiding as an internal guide methodically and meticulously.

I am highly indebted to all my Professors, Electronics and Communication Engineering for providing the necessary support.

I am greatly obligated to Dr. S. Sambhu Prasad, Principal, for permitting us to carry out my project work.

I render my deep sense of gratitude to Dr. P. Krishna Rao, Chairman, Dr. G. Raghu ram, Director and Sri. M. V. Harinatha Babu, Director (management).

I would also like to thank the Electronics and Communication Engineering Teaching and Non-Teaching staff for lending us their time to help us complete our work successfully.

I would also like to thank our parents and friends for their enduring encouragement and assistance whenever required.

HANITHA RAGHAVA D

(14A31D5701)

ABSTRACT

Design of low area-power efficient-rapid performance which is one of the vast areas of researching in VLSI system design. The carry select adder is one of the fast-performing adder used in data- processing and to perform efficient Arithmetic operations, where rapidly used in transportable mobile gadgets, wireless receivers and many bio medical appliances. Design of a high performance and high-density multiplier is presented. This multiplier is constructed by using the area, time and power efficient carry select adder. A fast carry select adder is used for the final two-operand adder. In this, the logical operations are involved in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA are analyzed to study the data dependence and to identify the redundant logical operations. We have dispensed with all the redundant logical operations present in the conventional CSLA and proposed a new logic formulation for CSLA. In this proposed scheme, the carry select (CS) operation is scheduled before the calculation of final-sum, which is different from the conventional approach. Bit patterns of two anticipating carry words (corresponding to Cin = 0 and 1) and fixed Cin bits are used for logic optimization of CS and generation units. An efficient CSLA design is obtained using optimized logic units. The proposed CSLA design involves significantly less area and delay than the recently proposed BEC-based CSLA. Due to the small carry-output delay, the proposed CSLA design is a good candidate for square-root (SQRT) CSLA. The proposed Architecture was synthesized using Xilinx ISE and power was analyzed using Xilinx Power Analyzer.

TABLE OF CONTENTS

Page No.

ACKNOWLEDGEMENT i

ABSTRACT ii

LIST OF TABLES vi

LIST OF FIGURES vii

LIST OF ACRONYMS ix

1. INTRODUCTION

1.1 Introduction to Scaling in VLSI 1

1.2 Motivation 1

1.3 Objective 1

1.4 Problem Statement 2

1.5 Problem Solution 2

1.6 Organization of Thesis 2

2. LITERATURE SURVEY

2.1 Introduction 4 2.2 Literature Review 5

2.3 Conclusion 8

3. ADDERS

3.1 Introduction 9

3.2 Basic Adders 9

3.3 Complex Adders 10

3.4 Comparison of Adders 14

3.5 CSLA Advantages and Disadvantages 15

4. DESIGN AND IMPLEMENTATION

4.1 Area and Delay evaluation of Basic Adder Blocks 16

4.2 Implementation of 16-bit CSLA 17

4.2.1 Area and Delay16-bit Regular SQRT CSLA 18

4.3 Implementation of 16-bit BEC-1Based CSLA 19

4.3.1 16-bit BEC-1Based SQRT CSLA 21

4.4 Architecture of Improved CSLA 23

4.4.1 Introduction 21

4.4.2 Implementation 23

4.4.3 16-Bit Implementation of Improved CSLA 25 4.5 Replacing Improved CSLA with Binary Adder 27

4.5.1 Introduction 27

4.5.2 Implementation 27

4.5.3 Conclusion 30

5. FPGA IMPLEMENTATION 5.1 Introduction 31

6. VERILOG

6.1 History of Verilog 34

6.2 Basic Concepts 34

6.3 Verilog Introduction 35

6.4 Verilog Features 35

6.5 Design Flow 35

6.6 Functional Verification and Testing 36

6.6.1 Logic Synthesis 36

6.7 Logical Verification and Testing 37

7. XILINX 38

7.1 Getting Started 38

7.2 Initiation 38

7.3 Creating a Project 39

7.4 Opening a Project 40

7.4.1 Creating a Verilog HDL input file for CLD 42

7.5 Reworking the Verilog Source file 43

7.6 Design Implementation and its Synthesis 44

7.7 Simulating and Viewing the output waveforms 45

7.7.1 Saving Simulation Results 46

8. RESULTS 47

8.1 Introduction 47

8.2 Simulation Output 47

8.3 RTL Schematic 49

CONCLUSION 51

FUTURE SCOPE 52

BIBLIOGRAPHY 53

LIST OF TABLES

Table 4.1 Delay and Area Count of the Basic blocks of CSLA 17

Table 4.2 Functional Table of 4-bit BEC 20

Table 4.3 Delay and Area count of SQRT CSLA groups 22

Table 4.4 Delay and Area count of modified SQRT CSLA groups 23

Table 4.5 Comparison of Different SQRT CSLA with proposed 26

Table 4.6 Number of components used in Modified CSLA 29

Table 4.7 Comparison of different CSLA with Modified CSLA 30

Table 5.1 Output values of SQRT CSLA 31

Table 5.2 Output Values of BEC based SQRT CSLA 32

Table 5.3 Overall SQRT LUT’s delay 32

LIST OF FIGURES

Fig.3.1 Half adder logic diagram 9

Fig.3.2 Schematic symbol for a 1-bit full adder 10

Fig.3.3 Block diagram of full-adder implementation via a pair of half-adders 10

Fig.3.4 4-bit Ripple carry adder 11

Fig.3.5 n-bit Carry Save Adder 12

Fig 3.6 Carry Skip Adder 12

Fig 3.7 Carry Select Adder 13

Fig 3.8 Carry Lookahead Adder 14

Fig 4.1 Delay and Area evaluation of XOR gate 16

Fig 4.2 CSLA basic building block 17

Fig 4.3 Regular 16-bit SQRT CSLA 18

Fig 4.4 Delay and Area evaluation of regular SQRT:

CSLA (a) group 2 and (b) group 3 (c) group 4 and (5) group 5 19

Fig 4.5 4-bit Binary to Excess 1 Converter 19

Fig 4.6 4-Bit BEC with 8:4 MUX 20

Fig 4.7 BEC based 16-bit SQRT CSLA

The parallel RCA with CIN = 1 is replaced with BEC 21

Fig 4.8 SQRT CSLA’s Area evaluation and Delay

(a) group 2 (b) group 3 (c) group 4 and (d) group 5 23

Fig 4.9 Proposed CSLA 24

Fig 4.10 Detailed Internal Structure of Improved Architecture 25

Fig.4.11 16-bit SQRT Improved CSLA 25

Fig 4.12 Shift and Add Multiplier 26

Fig 4.13 16-bit CSLA using Binary Adder 28

Fig 4.14 Internal structure of Binary Adder 28

Fig.6.1 VSLI Design Flow 36

Fig 7.1 Xilinx Project Navigator Window 40

Fig.7.2 Device and Design Flow of Project 41

Fig 7.3 Creating Verilog-HDL source file 42

Fig 7.4 Project Navigator in the Verilog Source code editor window 44

Fig 7.5 Design Implementing 45

Fig 7.6 Simulating the Design 46

LIST OF ACRONYMS

VLSI Very Large Scale Integration

BEC Binary to Excess

CSLA Carry Select Adder

SQRT CSLA Square root Carry Select Adder

RCA Ripple Carry Adder

CHAPTER 1

INTRODUCTION

1.1 INTRODUCTION TO SCALING IN VLSI

Today VLSI industry requires ultra-high speed, low chip area, low power consumption, portable processors. To fulfil the above requirements there is a need to scale the devices and device interconnects. This leads to Moore’s law of scaling in integrated circuits. Design of low power-area efficient-rapid performance in VLSI system design, where rapidly used in transportable mobile gadgets, wireless receivers and many bio medical appliances. A complex digital signal processing (DSP) framework involves several adders. An proficient adder design essentially enhances the performance of a complex DSP system.

1.2 MOTIVATION

For the past decades, the scaling of complex adders has been the driving force towards the technological advancement. An adder or summer performs addition of numbers, where adders placed a role in computers, processors where it is not only used in arithmetic logic units but used in many parts of processors to calculate addresses, table indices, and increment and decrement operations.

In many numerical representations adders can be constructed, binary to decimal or binary to excess-3 or binary adders. In 1’s and 2’s complement is being represent negative numbers, which modify adder into adder-subtractor. There are many types of adders such as half adders, full adders, ripple carry adder and carry select adders.

1.3 OBJECTIVE

The Carry Select Adder (CSLA) is one of the quick performing adder utilized in data- processing to perform proficient Arithmetic operations, where rapidly used in transportable mobile gadgets, wireless receivers and many bio medical appliances.

A CSLA is very fast and it is simultaneously capable of calculating all the input bits. Where CSLA uses a dual RCA to generate carry and sum using carry inputs 0 and 1. The CSLA has less propagation delay then ripple carry adder. Few attempts are made to reduce the dual RCA. The CSLA implementation with 16 bit SQRT- CSLA has less delay but size is more due to cascading network where it can perform parallel operations compared. Where as in BEC based CSLA there are less resources and more delay.

The objective is to implement 16 bit CSLA by replacing the BEC based CSLA with Binary adder with BEC-1, in order to diminish Area, Power and Delay. Finally, 16 bit Binary based CSLA is implemented, results are compared with different techniques proposed by different scholar.

1.4 PROBLEM STATEMENT

The performance optimization of 16 bit regular CSLA technique using dual RCA with carry input 1 and 0 where the number of gates increases area increases for two carry inputs. In order to reduce the number of bits for each full adder replacing the full adder with carry input Cin = 0 with the full adder in each ripple carry of 2-bit, 3-bit,4-bit etc. So hence reducing the area which was proposed by Youngjoon Kim and Lee-Sup Kim with an add-one circuit which is nothing but a multiplexer. Chang proposed a SQRT- CSLA to implement large bit- adders using less delay. Where the main objective is to provide parallel path where it helps in reducing the delay. Ramkumar and Kittur suggested a binary to binary excess-1 code, where the number of logic resources in the SQRT are reduced in this method but there is a marginal delay. Where another method, common Boolean logic based CSLA involves less resources but there is a long carry propagation delay which is equivalent to RCA. In order to decrease the power, delay and area the proposed method is implemented.

1.5 PROBLEM SOLUTION

In order to reduce the area, power and delay proposed a modified CSLA is introduced. Where instead of using n+1 BEC-1 adder, using a binary adder helps in reducing the gate count as well as area. Therefore, reducing the power as well when compared to binary to excess code 1. As the number of inputs reduces the overall delay also reduces. This modified CSLA which is similar to conventional CSLA, but replacing the n-bit ripple carry adder with the n-bit binary adder followed by a OR gate as the carry input to the next stage. Therefore, implementing a proposed CSLA is the best solution to reduce overall delay, power and area.

1.6 ORGANISATION OF THESIS

The report is organized into 5 chapters.

CHAPTER-1: INTRODUCTION

This chapter introduces scaling issues in VLSI circuits, purpose for employing alternate technology and project objective. Finally, this chapter explains organization of this thesis.

CHAPTER-2: LITERATURE SURVEY

This chapter gives an overview on the background work on adder’s technology and its specifications. It also discusses the importance and consideration of Carry select adder as an operational circuit and different papers which focuses on the need for overcoming the device scaling effects and improving device operation.

CHAPTER-3: PROPOSED METHOD

This chapter introduces the Binary adder replacing BEC-1 implementation to decrease the area, delay and power. Firstly, the CSLA is implemented in stages of 8 bit, 16 bit. Where this technique is implemented with less number of inputs, and faster response. Finally, the evaluation of proposed methodology, with Xilinx simulation is discussed.

CHAPTER-4: RESULTS AND DISCUSSION

This chapter explores the different techniques of CSLA and comparison of conventional CSLA, BEC based CSLA and proposed method. The experimental results are discussed in stages of 8bit, 16 bit CSLA of all the different CSLA’s. The comparisons are assessed in terms of area in micro meter square (µm2), power in micro watt (µW) and delay in nano seconds (ns).

CHAPTER-5: CONCLUSION AND FUTURE SCOPE

This chapter gives the conclusion of the thesis and future scope.

CHAPTER 2

LITERATURE SURVEY

2.1 INTRODUCTION

Adders are of major significance in a wide variety of computerized frameworks, a few sorts of quick adders exist yet including quick utilizing low area and power is as yet difficult. In digital adders, the speed of addition is limited by the time required to propagate a carry through adder. So, the CSLA is used in many computational systems to alleviate the problem of carry propagation delay. So many papers were published on this with several examples of such adders and many efficient implementations were also done.

In 1962, O.J. Bedrij described the extremely fast digital adder with sum selection and multiple-radix carry. He compared the amount of hardware and the logical delay for a 100-bit ripple-carry adder and a carry-select adder. The issue of carry-propagation delay was overcome by independently generating multiple-radix carries and utilizing these carries to select between simultaneously generated sums. In this adder system, the addend and augend were isolated into sub addend and sub augend segments that were added twice to produce two sub sums. One addition was finished with a carry digit forced into each section, and the other addition combined the operands without the constrained carry digit. The determination of the correct sub sum from each of the adder sections relied upon whether or not there actually was a carry into that adder section.

There are many carry select adder approaches available but most of them use ripple carry adder. T.Y. Chang and M.J. Hsiao, suggested that instead of using dual ripple carry adders, a carry select adder scheme using an add one circuit to replace one ripple carry adder requires 29.2% fewer transistors with a speed penalty of 5.9% for bit length n=64. If speed was important for this 64-bit adder, then two of carry-select adder blocks could be substituted by the proposed scheme with a 6.3% area saving and the same speed. The Youngjoon Kim and Lee-Sup Kim suggested that a carry-select adder could be implemented by using single ripple carry adder and an add-one circuit instead of using dual ripple-carry adders. They proposed a new add-one circuit using the first zero finding circuit and multiplexers to reduce the area and power with no speed penalty. For n=64 bit, this new carry-select adder requires 38% fewer transistors than the dual ripple-carry carry select adder and 29 percent fewer transistors than Chang\'s carry-select adder using single ripple carry adder. This new 64b adder using a 0.25 um CMOS technology had 3.45 ns delay time at 2.5 V power supply. Behnam Amelifard et.al, suggested a new adder called carry select adder with sharing (CSAS) which was area efficient but the delay was more.

2.2 LITERATURE REVIEW

It includes the survey on different techniques in different papers published by different authors which leads to proposed methodology.

It includes the survey on different techniques in different papers published by different authors which leads to proposed methodology.

[1] O. J. Bedrij, ―carry-select adder, ire trans. Electron. Comput. pp. 340–344, 1962:

Bedrij used AND, OR and inverter (AOI) for implementation of an XOR gate. The primary idea of this work is to use Binary to Adder 1 Encoder (BA1E) instead of Ripple Carry Adder (RCA) with Cin=1 in the CSLA to achieve low device utilization and power consumption. The advantage of this BA1E is, logic comes from the lesser number of logic gates than the n-bit full adder structure. To overcome the problem of carry-propagation delay, he described the delay and area by evaluating in different methodologies. And therefore, it is used for efficient for VSLI hardware implementation.

[2] B. Ram Kumar, H.M. kittur, and p. M. Kannan, ―asic implementation of modified faster carry save adder, ‖ eur. J. Sci. Res., vol. 42, no. 1, pp. 53–58, 2010:

A low power with high speed CSLA is used in this project. In DSP processor, adder circuit is the main building block. The main problem that digital adders suffer is the carry propagation delay. CSLA is used in computing unit to solve this problem. In order to reduce power of the regular CSLA, BEC logic is used instead of RCA with Cin = 1. An n+1 bit BEC is required to replace an n-bit RCA. To reduce the power of regular CSLA a simple gate level modification is required. The great advantage in terms of area and power is to reduce the number of gates in this work. With slight increase in delay, this design has reduced area and power as compared to the regular SQRT CSLA. These results illustrate that, CSLA has better performance than the conventional CSLA.

[3] T. Y. Ceiang and m. J. Hsiao, ―carry-select adder using single Ripple Carry Adder, ‖ electron. Lett. vol. 34, no. 22, pp. 2101–2103, Oct. 1998:

Due to the rapid change in the cellular industry, not only the faster arithmetic unit but also less area and low power arithmetic units are needed. He proposed an efficient method which replaces the BEC using D latch. This CSLA architecture has been developed using BEC. In VSLI design, we can reduce the silicon amount area by using BEC logic. To select the actual calculated values of the output carry and sum, least significant bit stage is used. Multiplexer does the selection in this process. One input to the mux goes from the RCA with Cin=0 and other input from the BEC. But, by using BEC method the main disadvantage is the delay is increasing compared to the regular CSLA. The Binary to excess-1 circuit is replaced by D-latch with enable signal. In order to reduce the area, power consumption and delay in this method only one adder is used instead of two separate adders. Hence, it is clear that BEC structure reduces the area and power.

[4] Akhilesh Tyagi, ―A Reduced-Area Scheme for Carry-Select Adders‖ Electron. Lett, vol. 34, no. 22, pp. 2101–2103, Oct. 1993:

He acquainted plan to generate carry bits with block Cin = 1 from the carries of a block with block Cin=0. Here he used a simple combinational circuit instead of a multiplexer and a RCA Cin=1 structure, which consists of AND and XOR gates. Based on this modified architecture 8-, 16-, 32- and 64- bit square root CSLA (SQRT CSLA) have been developed and compared with the regular BEC SQRT CSLA architecture. Implementing in FPGA kit, the performance factors of this design are evaluated in the terms of delay, area, power and their products by simulation tool. In order to reduce the power consumption of data path we need to reduce Area of the adder. And hence the area and power consumption is also reduced.

[5] Y. Kim and l.-s. Kim, ―64-bit carry-select adder with reduced area, ‖ Electron. Lett. vol. 37, no. 10, pp. 614–615, may 2001:

The proposed design’s performance can be estimated compared to the common ones in terms of delay, area and synthesis, are implemented in Xilinx FPGA. By using two independent RCA the area will increase which in turn the delay also increases. The main advantage of BEC logic is the number of gates will be reduced than the full adder structure. The assessment strategy of deferral and region considers every one of the entryways to be comprised of AND, OR, and Inverter, each having postponement of 1 unit and region to 1 unit. To overcome this problem, n-bit binary to excess-1 code converters (BEC) is use to improve the speed of addition. By performing the additions in parallel and decreasing the maximum carry delay, the speed of the CSLA can be improved from 40% to 90%. Using Verilog-HDL (Modelsim) this implemented design has been simulated.

[6] J. M. Rabaey, digital integrated circuits—a design perspective. Upper saddle river, nj: prentice-hall, 2001:

By sharing a common Boolean logic, we proposed an area efficient CSLA. In this method, duplicate adder cells are used in conventional unit of CSLA. After the simplification of logic, the duplicate adder cells can be removed. Sharing the partial circuit, we need only one XOR gate and one inverter gate in each summation operation and one AND gate and one inverter gate in each carry-out operation. According to the logic state of Cin signal, we can select the correct output result through multiplexer. Nearly, with the same transistor count, power consumption but with faster accuracy and lower PDP our area efficient can operate compared to carry ripple adder. In this way, we can reduce the transistor count in a 32-bit CSLA.

[7] Y. He, c. H. Chang, and J. GU, ―an area efficient 64-bit square root Carry-select adder for low power applications,‖ in proc. IEEE int. Symp. Circuits syst., 2005, vol. 4, pp. 4082–4085:

To perform fast arithmetic functions, CSLA is one of the most accurate adders used in many data-processing processors. This method first uses the implementation of adder and then the excess one adder. The problem raised in CSLA is not an area efficient but in delay. Because of using multiple pairs of RCA to generate the partial sum and carry which are selected by the multiplexer. The time delay will improve greatly by the extension of linear CSLA. Duplication of adders is implemented which is the main disadvantage in the SQRT CSLA. To overcome this disadvantage is, by using BEC for RCA with Cin =1 to optimize the area and delay. Duplication of adders can be removed after the partial logic is taken. Only with slight delay in the modified design will reduce area and power as compared to the regular SQRT CSLA. Based on this modification of 8, 16, 32, 64 and 128-bit SQRT CSLA architecture and simulation will be developed. The simulation is performed by using Modelsim and synthesis is carried on Xilinx ISE 12.2.

2.6 CONCLUSION

From the literature survey, Carry select adder offers better delay performance among all the digital adders. Study of different adders, complex adders gives performance comparison of both with varying parameters. With reference to these Regular CSLA, Conventional CSLA and BEC based CSLA implementation is observed and new method performance is stated in the proposed method.

CHAPTER 3

ADDERS

3.1 INTRODUCTION

An adder or summer performs addition of numbers, where adders placed a role in computers, processors where it is not only used in arithmetic logic units but used in many parts of processors to calculate addresses, table indices, and increment and decrement operations. In many numerical representations adders can be constructed as, binary to decimal or binary to excess-3 or binary adders. In 1’s and 2’s complement is being represent negative numbers, which modify adder into adder-subtractor. There are many types of adders such as half adders, full adders, ripple carry adder and carry select adders.

3.2 Basic Adders:

• Half Adder

The half adder adds two binary digits of inputs A and B to produce outputs of carry (C) and sum (S). Where the signal of the carry represents the overflow, which can be added to the next digit of multi digit addition. The below shows the half-adder design, where sum (S) is generated by XOR gate and carry (C) is generated by AND gate.

Fig 3.1 Half adder logic diagram

OR gate’s addition will combine their carry outputs, to make a full adder two half adders could be combined.

• Full Adder

The FA is combination of two half adders followed by an OR gate. Where it adds three input binary inputs to produce sum (S) and carry (Cout). Where A, B and Cin are the inputs to the full adder. The only difference between half adder and full adder is two bit and three-bit binary input.

Fig 3.2 Schematic circuit for a 1-bit full adder

By connecting A and B, two half adders one full adder can be constructed to the input of one half adder and piping the sum from that to an input to the second adder, connecting Ci to the other input and OR the two carry outputs. The full adder’s critical path runs through both XOR-gates and ends at the sum bit S.

Fig 3.3 Block diagram of full-adder implementation via a pair of half-adders

3.3 Complex Adders:

• Ripple-Carry Adder (RCA)

The RCA is designed by cascading n-full adders blocks in series. For the addition of two binary digits one full adder is responsible at any stage of the ripple carry. The Cout is one stage fed directly to the Cin of the next stage. In spite, it is a simple adder it can be utilized to add unhindered bit length numbers. In either case, it is not very efficient when large bit numbers are utilized. Amongst the most serious drawbacks is, the delay increases along with the bit length. When a carry signal transition ripples through all the stages of adder chain from the least significant bit to most significant bit, is the worst-case delay of the ripple carry adder. Example, this ripple carry adder can create a multiple full adder to add N-bit numbers. Where the carry generated by the (N-1) bit is the carry input to this full adder or in other words the carry out (Cout) of the previous adder is the carry input (Cin) of the present full adder. This is so called as ripple-carry adder, where each stage the carry bit ripples to the next full adder. Where the first full adder of Cin =0 replaced with half adder.

Fig 3.4 4-bit Ripple carry adder

The ripple-carry adder is simple, which allows for fast design time. However, the ripple-carry adder has much delay, because each full adder has to wait for the carry bit to calculate from previous full adder.

• Carry Save Adder

A carry-save adder is one of the advanced adders, utilized in system microarchitecture to compute the sum of three or more n-bit numbers in binary. It varies from other digital adders, in that output two numbers of the same dimensions as the inputs, one which is a consecutive of partial sum bits and another which is a consecutive of carry bits. Carry save adder reduces the sum of 4 numbers to the sum of 3 numbers. The propagation delay will be at least 3 gates regarding the number of bits. The CSA consists of n full adders and each of them computes a single sum and carries bits to the corresponding adders which consists of the three input numbers. By shifting the carry sequence to left by one place and adding a 0 to the initial of the partial sum sequence and summing this sequence with RCA will produce the resulting n + 1-bit value. Indefinitely, this process can be continued by adding an input to each stage of full adders without any carry in the intermediate. In a binary tree structure, these stages can be arranged with a cumulative postponement in the number of inputs that can be added, and invariant of the number of bits per input. One of the main application is, multiplier architecture which is used for proficient CMOS implementation of the wider variety of algorithms for rapid digital signal processing. To speed up the carry propagation in the array, CSA is applied in the partial product line of array multipliers.

Fig 3.5 n-bit Carry Save Adder

• Carry Skip Adder or Bypass Adder

Carry Skip Adder (CSkA) is used to skip the logic in the propagation of carry bit. The architecture of CSkA is designed in the way to speed up the addition operation, by adding a propagation of carry bit to the initial part of the adder. A CSkA consists of a simple ripple carry adder linked with a speed up carry chain known as skip chain. When adding of large number of bits takes place, CSkA computes fast when compared to RCA. With a simple and regular design, carry skip adder has O(√n) delay which is beneficial in terms of delay. This chain characterizes the distribution of ripple carry blocks, which compose the skip adder. A CSkA is intended to increase speed in a wide adder by aiding the propagation of a carry bit to the initial part of the adder. Actually, the ripple carry adder computes faster for smaller values of N. Now-a-days, the criteria of industries are most desktop PC’s utilized word lengths of 32 bits as multimedia processors, makes the carry skip structure more fascinating. Depending on technology considerations, the RCA and CSkA is applied and it is normally between 4 to 8 bits.

As in a RCA, each and every full adder cell has to wait for the incoming carry before an outgoing carry can be generated. This reliance can be dispensed by presenting an additional bypass (skip) to speed up the operation of the adder.

Fig 3.6 Carry Skip Adder

• Carry Select Adder

In Carry Save Adder (CSA), 3 bits are added simultaneously at a time. In this case, the carry is not promoted through the stages. Instead of promoting, the carry is stored in present stage, and renovated as addend value in the next stage. Hence, in this case, the delay is reduced due to the carry. There are many different cases where it is desired to add more than 2 numbers together. The linear way is, adding together m numbers (all n bits) is to add the first two numbers, then adding that sum to the next and so on. The carry select adder is constructed by cascading two ripple carry adders with a multiplexer. The ripple carry adder consists of full adder and each full adder starts its summation waiting for carry out signal. Therefore, the transferring path of the carry determines the delay in ripple carry adder. As determined, the way of transferring N-bit carry is the typical way in an N-bit full adder. If N will increase the delay in ripple carry adder will also increase simultaneously. Carry select adder is used in order to improve the shortcoming of carry ripple adder to remove the linear dependency between delay time of computing and input word length.

Fig 3.7 Carry Select Adder

• Carry Look Ahead Adder

Carry Look Ahead (CLA) can deduct the transferring delay occurred in the congruent adders. This adder also decreases delay of the carry by reducing the number of gates through which the carry signal must propagate. Carry look Ahead adder is implemented to overcome the latency caused by the rippling effect of the carry bits. The principle of carry look Ahead adder is based on, looking at the lower order bits of the augends and addend if a higher order carry is generated. Carry look ahead adder relies upon two things: Calculating each digit position, whether the position is going to transfer a carry if one originates from the right and combining these calculated values that can be able to infer quickly whether every digit’s group is going to transfer a carry that comes in from the right. Just as in ripple carry system, the total effect that carriers start by propagating slowly through each 4-bit group, then moves 4 times faster, leaping from one to another look ahead carry unit. Finally, that receives a carry it propagates slowly within the digits and within that group. There are faster ways to add binary numbers using carry look ahead adders and to reduce the computing time. By creating two signals P and G known to be Carry Propagator and Carry Generator, the carry propagator is transferred to the next level. Whereas, the carry generator is used to generate the output carry regarding to input carry.

Fig 3.8 Carry Lookahead Adder

3.4 Comparison of Adders:

The comparison has been performed among all the adders for high accuracy, less area and power. According to the results which are shown, the adder topology which has the best compromise between high accuracy, less area and power are carry look-ahead and carry increment adders and they are suitable for high performance and low-power circuits. With the penalty of area, carry select adder and carry save adder are the fastest. With the least gate count and maximum delay ripple carry adder, carry skip and carry bypass adder are the simple topologies which are suitable for low power appliances.

We have proposed a new logic formulation for the CSLA and eliminated all the redundant logic operations of the conventional CSLA. Based on the proposed scheme, carry words corresponding to input-carry 0 and 1 are generated by the CSLA. To reduce the area and power of CSLA architecture is the simplest approach. Great advantage in the reduction of area and also the power is to reduce the number of gates of this work offers. The renovated architecture of CSLA is low area and power, simple and efficient for VLSI hardware implementation.

Reason behind choosing CSLA

Carry select adder is used in order to improve the shortcoming of carry ripple adder to remove the linear dependency between delay time of computing and input word length. The main advantage in the decreasing of area and also the power is to reduce the number of gates of this work offers. When compared with delay in some adder and area in some adder this method has more order in which the system performs the most.

3.5 CSLA Advantages and Disadvantages:

Advantages:

• Carry select adder is very fast and able to calculate all the input bits approximately simultaneously.

• In digital adders, the speed of addition is limited by the time required to propagate a carry through the carry select adder.

• Low power consumption.

• Less complexity (less area).

• More speed compared to regular CSLA.

Disadvantages:

• More costly than other adders.

• Designing is complex than simple adders.

Carry Select Adder Applications:

• Carry select adder is used in many data-processing processors to perform fast arithmetic functions.

• The carry select adder is used in many computational systems to alleviate the problem of carry propagation delay by the independently generating multiple carriers and then select a carry to generate the sum.

• High speed multiplications.

• Advanced microprocessors design.

• Digital signal processing.

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