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  • Published on: 7th September 2019
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Introduction

Due to shrinking transistor sizes, the density of ICs roughly doubles every year as anticipated by Moore's law. These advancements saw a change from computation dominant designs to communication dominant designs incorporating very large number of simple cores. A lot of conventional interconnect schemes like point to point, buses & crossbars are available to interconnect fewer number of cores. To achieve fast & efficient communication by point to point communication, wire density is a constraint for adapting them to many core architectures. Additionally, buses are less complex in design, and they deal with scalability & arbitration issues along with bandwidth bottleneck as the cores count increases.

Likewise area & power requirements of a crossbar limits its applicability. Hence, in various core architectures like Chip Multiprocessors & Multi-processor System-on-Chip, rose the need for an efficient communication as the traditional solutions fails to handle the communication challenges. So, a new approach to replace the conventional interconnection techniques was needed. This led to the development of network-on-chip (NoC). NoC gives a structured & scalable solution to communication problems with its features such as high bandwidth, low latency, and scalability. NoC also provides communication parallelism by facilitating pipelining regardless of network sizes. Figure 1 shows the change in the trend of on chip connection

Figure 1 Trends of on-Chip connection

Network on Chip

Network on chip is the best approach against the conventional way of interconnection. In this, instead of having a connection between every IP blocks, a network is established within the chip & each IP acts as a node in this network. A computing node is associated with a router or switch through a network interface, & routers/switches are connected with links as shown in Figure 2.The entire communication happens through this established network. This communication can be circuit based or packet based. There is a physical structure of this interconnection which forms a suitable topology. Once the topology is formed, routing techniques are utilized to route the packets from one node to another. Figure 3 shows a typical router.

Fig. 2: Components of interconnection networks

A classic router or switch provides input buffers, an arbiter, a crossbar switch & an output registers. Since wormhole switching or virtual cut through switching is commonly used, most of the routers have a pipelined micro-architecture with 3-5 stages. These routing techniques are specifically designed for NoC & are preferred to be deadlock free.

Fig. 3: The typical router structure

Topologies in Network on Chip

The striking aspect of interconnection networks is their wide variation of connecting structure. As shown in Figure 4, there are divided into 2 different classes: direct & indirect. Direct interconnection network uses a router for each node, & a router is connected with each other directly as shown in Figure 2, whereas in indirect networks the network interfaces or routers are connected through switches. Traditional topologies like mesh, torus, and fat-tree have been widely utilized, while others use high radix topology with a numerous links like flatten butterfly or dragonfly. New standard topologies have been proposed for NoCs. Moreover, topologies with random short-cut links also received consideration for interconnection due there attributes like bisection bandwidth, diameter & degree. Uniformity, fault tolerance, extendibility & embeddability are additionally important attributes of topologies.

Fig. 4: Various topologies

Router Architecture

NOC architectures are based on packet switched networks which has led to new & efficient principles for design of routers for NOC. Routers implement various functionalities from simple switching to intelligent routing. As systems are constrained by area & power consumption, but still need high data rates, routers must be designed based on hardware usage. For circuit-switched networks, routers may be designed with no queuing. For packet switching, some amount of buffering is needed, to support burst data transfers. Such usage originate in applications such as video streaming. Buffers can be provided at the input, at the output, or at both input & output. Different designs & implementations of router architectures based on different routing strategies have been proposed. Wolkotte et al. proposed a circuit switched router architecture for NOC, while Dally & Towles proposed a packet switched router architecture.

Routing in Network on Chip

Figure 5. Routing algorithms.

Routing algorithm decides the route from the source node to the destination node. Routing algorithms are ordered in various ways, as shown in Figure 5. In unicast routing, the packets have a single destination, while in case of multicast routing, the packets have multiple destinations. For on-chip communication, unicast routing strategies seem to be a practical approach due to the presence of point-to-point communication links among various components inside a chip.

Challenges

 Despite the fact that NoC is the most practical solution to the traditional on chip interconnection, there are specific issues which exist in this kind of architecture. Some of these shortfalls are stated below.

Links: The use of serial or parallel links for data transfer through the network has always be an issue in NoC. Parallel links lessen power dissipation but it uses buffer based architecture consuming more area. Whereas, serial links saves area, reduces interferences & noise but needs serializer & de-serializer circuits for transport of data.

Interconnect Optimization: Communication in NoC occurs through modules connected via a network of routers through long links. Optimizing these links is very important for better system performance. Though use of repeaters solves this issue but at the cost of using more area on the chip.

The advances in silicon Nano photonics created new opportunities for on-chip networks. To efficiently use the benefits of Nano photonics, researchers had proposed Firefly, a hybrid, hierarchical network architecture. Firefly consists of clusters of nodes that are connected using conventional, electrical signaling while the inter-cluster communication is done using Nano photonics which exploits the benefits of electrical signaling for short communication, while Nano photonics is used only for global communication, but now it can be used to realize an efficient on chip network.

Power Consumption Leakage: In NoC the link utilization differ & in many cases is very low. The networks are designed so as to keep redundant links which are not often utilized. These low utilized links prevent the routed packets from being misrouted & also prevents collision. But even when the links are ideal, they consume power resulting in leakage due to their small size. This issue needs to be addressed so that NoC architectures are more effective.

To tackle the problem, an on-chip communication infrastructure based on a network-on-chip architecture & developed a hybrid mechanism to transfer data among IP cores by taking advantages of both wired & wireless communications. By using on-chip antennas, we can provide on-chip wireless communication to transfer data across long distances & minimize transfer latency & energy dissipation. A wireless network-on-chip architecture was designed, the experimental results showed significant improvement in energy dissipation, transfer latency, network throughput.

However as the chip shrinks the power ratio between link & router increase making link more power hungry than routers. Different encoding techniques are proposed to reduce the power in reference to the bus based architecture. Bus invert method can be applied to encode the randomly distributed patterns. This encoding scheme is developed by taking the both factor self-switching & the cross talk into consideration. The encoder & decoder are placed in the network interface of the routed network. The first stage rearranges the data stream in way that the transition in each link is reduced, while the second stage inverts the data depending on the contribution of the cross couple activity of power dissipation in the link. The proposed encoding scheme can be applied to the wormhole routed network as the interleaving of flits are not allowed.

Moreover, NoCs can consume a considerable share of chip power. Diverse applications are executed in these multicore, where each application imposes a unique load on the NoC. To implement a NoC which is Energy & Delay efficient, we combine multiple Voltage-frequency optimized routers for each node for efficient NoC for Dark Silicon chips. A generic NoC with routers designed for different VF levels, which are distributed across the chip. At runtime, depending on application profile, combination of these VF optimized routers form constantly changing energy efficient NoC chip. These can reduce the Energy Delay product (EDP) up to 46% for widely differing workloads.

Also the proposed iDEAL, a low-power area-efficient NoC architecture works by reducing the number of buffers within the router. This uses adaptive dual-function links capable of data transmission as well as data storage when required. Simulation results revealed that by reducing router buffer size to half and using the adaptive dual function links achieves approximately 40% savings in buffer power, 30% savings in network power and 41% savings in the router area, with only a minimal performance tradeoff.

Research directions

Software defined networks-on-chip: In the past, any change of the network protocol usually required replacing the hardware, since the protocol definition was closely coupled with the hardware in the form of specific IC's. The high hardware replacement cost is unacceptable, & was not able to catch up to the rapid updating technology. Moreover, to satisfy different requirements, application-specific network-on-chip design introduces overhead of designing network with different configurations & interconnection. These steps require significant design time & need to verify network components & their communications for each design. To deal with the hardware redesign & replacement problems in the computer network, the software-defined networking (SDN) promises a flexible solution for computer networks. The Open Flow protocol that is used to implement SDN provided a programmable interface to manage network structure & traffic. The idea of SDN also improve the flexibility of network-on-chip to adapt to the requirements of applications with programmability.

Even though, there are hardware programmable solutions, the trade-off between hardware performance degradation & the programming flexibility is inevitable. Moreover, the programmable hardware such as FGPA gives scope for bus  & interface design, and designer could implement communication mechanisms as they would, which result in incompatibility. The software defined method offer a solution to address this challenge with the common API between control & data forwarding plane. Therefore, software is responsible of control logic while the hardware is only responsible for data forwarding, so that the communication control logic is decoupled from hardware design. If the designers are to change the communication scheme, only the control logic is modified with software, while the underlying on-chip network remains unchanged.

But to be actually deployed it on chip, more details have to be considered for API implementation and standardization between control plane and data forwarding plane as the Open Flow specification does. With its programming flexibility and obvious advantages in performance and energy consumption, there will be more research to be done in the future.

3D NOC: The advantage of 3D NoC is that it can greatly reduce the diameter of the topology for NoC leading to reduction in packet transfer time & latency. Moreover the increasing the adaptively for information routing can also help in achieving the desired throughput.

Fig 5: 4x4x4 3D-Mesh based NoC

A 3D communication architecture for the NoC can be established by large portioning a 2D die into smaller segments & stacking them. The decrease in diameter of the topology for 3D architecture has a great advantage of reducing the wiring or channel on the chip. Figure 5 exhibits an example of 4x4x4 3D-Mesh based NoC.

Three-dimensional (3D) integration provides the benefits of better performance, lower power consumption, & increased bandwidth through the use of vertical interconnects & 3D stacking. The vertical interconnects enable the design of a high bandwidth & energy-efficient network-based 3D network-on-Chip for massive multicore platforms.

The 3D integration using TSV (through-silicon-via) is an emerging model and it can be classified into one of the two following categories: monolithic approach and stacking approach. The first involves a sequential device process, where the front end processing (building the device layer) is repeated on a single wafer to form multiple active device layers before the backend processing builds interconnects in devices. The second (which can be wafer-to-wafer, die-to-wafer, and die-to-die) processes each active device layer separately using conventional fabrication techniques. These multiple device layers are then assembled to build up 3D ICs using bonding technology. These dies can be bonded face-to-face (F2F) or face-to-back (F2B). However research is needed as these type of NoC topology design should be thoroughly studied and respective topologies for different 3D technologies should be identified with respect to the performance, power, thermal, and reliability optimizations.

Conclusion:

Network on chip addresses major of the issues of on-chip interconnections making it a promising alternative to the current interconnection techniques. It provides a wide scope in future on-chip architecture. It has also provided huge opportunities of research and implementation in chip technology. In this paper we have provided a brief introduction to network-on chip, its major challenges and discussed about Three-dimensional integration, software defined networks and how they can help in efficient design .Each of these emerging interconnect models, could offer remarkable advantages. However, in order to harvest their potential, more research is necessary in various challenging areas such as system architecture, IC design & fabrication and CAD tool development.

References:

1. Hridoy Jyoti Mahanta, Abhijit Biswas, Md. Anwar Hussain "Networks on Chip: The New Trend of On Chip Interconnection" 2014 Fourth International Conference on Communication Systems and Network Technologies.

2. Liu Cong, Wang Wen, Wang Zhiying "A Configurable, Programmable and Software-Defined Network on Chip" 2014 IEEE Workshop on Advanced Research and Technology in Industry Applications (WARTIA).

3. Hideharu Amano "Tutorial: Introduction to Interconnection Networks - From System Area Network to Network on Chips" 2013 First International Symposium on Computing and Networking.

4. Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh "A Wireless Network-on-Chip Design for Multicore Platforms" 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing.

5. Ankur Agarwal, Cyril Iskander, Ravi Shankar "Survey of Network on Chip (NoC) Architectures & Contributions" Journal of Engineering, computing and architecture Volume 3, Issue 1, 2009

6. Haseeb Bokhari,Haris Javaid, Muhammad Shafique, Jorg Henkel,Sri Parameswaran "Malleable NoC: Dark Silicon Inspired Adaptable Network-on-Chip" 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

7. Naveen Choudhary "Network-on-Chip: A New SoC Communication Infrastructure Paradigm" International Journal of Soft Computing and Engineering (IJSCE) January 2012

8. Yan Pan, Prabhat Kumar, John Kim', Gokhan Memik, Yu Zhang, Alok Choudhary "Firefly: Illuminating Future Network-on-Chip with Nanophotonics"

9. Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri "iDEAL: Inter-Router Dual-function Energy and Area-efficient Links for Network-on-Chip (NoC) Architectures" International Symposium on Computer Architecture

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