IMPLEMENTATION OF SDC USING I2C MULTI MASTER-MULTI SLAVE WITH WISHBONE SIGNAL
Nandini.Gadamchetty, M Tech (Final year),DECS, NBKRIST, Vidyanagar.
Dr.K.Nagi Reddy, professor, Electronics and communication, NBKRIST,Vidyanagar.
I2C Multi Master with Multi Slave is designed from a bidirectional data serial bus containing bidirectional data line i.e. Serial Data Line (SDA) and Serial Clock Line (SCL) along with Wishbone Signal.
I2C protocol has the ability to support multiple masters and provides an efficient method of data exchange between devices. This is very much useful protocol for faster devices to communicate with slower devices and each other without data loss. With the use of this protocol a serious problem arises resulting to overlapping of signals. To overcome such problems, a special signal called WishBone signal is used.
The complete module is modeled in Verilog HDL and synthesized in Xilinx 13.2i, also simulated in ModelSim 6.4a.
Keywords: I2C (or IIC, inter integrated circuit), WishBone, SCL (Serial Clock Line), SDA (Serial Data Line), Master, Slave, Xilinx, ModelSim 6.4a.
In the world of serial data communication , I2C (Inter Integrated Circuit) bus has become a de-facto standard for short-distance communication among ICs. The I2C  bus uses two bi-directional open-drain wires with pull-up resistors. There is no strict baud rate requirement as with other communication standards. The true multi master bus allows protection of data corruption if multiple masters initiate data transfer at same time. Many other features of the I2C bus provide efficient and flexible means for control functions that do not require high speed data transfer, and for applications that require a small amount of data exchange.
The WISHBONE Bus interface is a free, open-source standard in digital systems that require usage of IP cores. This bus interfaces reuses IP by defining a common interface among IP cores. This provides portability for the system.
In this project, we are implementing multi master and multi slave I2C bus protocol with WISHBONE signal for interfacing low speed peripheral devices on FPGA . It is also the best bus for the control applications, where devices may have to be added or removed from the system. I2C protocol can also be used for communication between multiple circuit boards in equipments with or without using a shielded cable depending on the distance and speed of data transfer. I2C bus is a medium for communication where master controller  is used to send and receive data to and from the slave. The low speed peripheral, is interfaced with I2C master bus.Fig-1 shows the I2C bus system with multi master and multi slave.
When using multiple master Arbitration and clock stretching need to considered. Arbitration decides which master is going to rule the bus.
The synopsis of the paper is as follows: In section 2, we discussed I2C protocol of our proposed design which also presents module description for our proposed system. In section 3, we present the software implementation along with algorithm and flow chart. Finally, concluded in session 4.
Fig-1: I/O diagram of I2C multi master and multi slave bus controller.
2. PROPOSED WORK:
The I2C bus is a multi-master bus that supports a multi-master mode. This allows more than one device capable of controlling the bus that is connected to it. Each I2C device is recognized by a unique address and can operate as either transmitter or receiver depending on the function of the device. In addition to being a transmitter or receiver, devices connected to the I2C bus can also be considered as master or slave when performing data transfers. A master device is the device that initiates a data transfer on the bus and generates the clock signals to permit that transfer. During this transfer, any device addressed by this master is considered as a slave.
I2C bus has only two wires and they are SDA (serial data line) and SCL (serial clock line). SCL acts as a clock line for I2C bus where SDA acts as a data line.
Fig-2:a)'START' sequence b) 'STOP' sequence
The SCL and SDA lines are connected to all devices on the I2C bus. As both SCL and SDA lines are "open drain' sources. The I2C bus is said to be idle when both SCL and SDA are at logic 1 level. When the master (controller) wishes to transmit data to a slave, it begins by issuing a start sequence on the I2C bus, which is a high to low transition on the SDA line while the SCL line is high as shown in Fig-2(a). The bus is considered to be busy after the START condition.
In Fig-2(b) which shows the STOP sequence, where the SDA line is driven low while SCL line is high. This signal ends the transaction with the slave device.
The design has four main modules as shown in Fig-3. This includes one top-level module and three lower-level modules, the byte command module and a bit command module.
In addition to connecting all the functional blocks together, this module generates byte-wide data, acknowledgement, and interrupt for the WISHBONE interface
Fig-3: Block diagram of I2C module
Depending on the parameter ARST_LVL, the reset polarity is determined and distributed to all the modules.
The microcontroller issues commands and data through the WISHBONE interface in byte format. The information is fed into the Byte Command Controller module and is translated into I2C sequences required for a byte transfer. This module includes a state machine, as shown in Figure 4, to handle normal I2C transfer sequences.
Bit command controller module directly controls the I2C bus, SCL and SDA lines, by generating the correct sequences for START, STOP, Repeated START, READ, and WRITE commands. Each bit operation is divided into five (5 x SCL frequency) clock cycles (idle, A, B, C, and D), except for the START command that has six clock cycles. This ensures that the logical relationship between the SCL and SDA lines meets the I2C requirement for these critical commands. The internal clock running at 5 x SCL frequencies is used for the registers in this module.
By the nature of open-drain signal, the I2C provides clock synchronization through a wired-AND connection on the SCL line. This clock synchronization capability can be used as a handshake between the slave and master I2C devices. By holding the SCL line low, the slave device tells the master to slow down the data transfer until the slave device is ready. This design detects the SCL line to determine if the line is being held.
3. SOFTWARE IMPLEMENTATION:
I2C bus is a medium for communication where master controller is used to send or receive data to and from slave and it is developed by Philips.
I2C multi master with multi slave is designed using Verilog HDL  based on Finite State Machine (FSM). There are several states in obtaining the result. The Algorithm for this design is as follows:
1) IDLE: When SDA and SCL are HIGH; it will stay in idle and will not perform any operation.
2) START: To start I2C operation master will generate it by transmitting SDA from HIGH to LOW when SCL is HIGH.
3) WRITE: Master will send 8 bits of data from those 8 bits, in that 7 bits are address and 8th bit will be zero as it is a read operation.
4) If the address sent by master will be matched with slave address then slave will generate ACK pulse.
5) After reception of ACK pulse master will send 8 bit register address , if again it is matched then slave will again generate ACK pulse.
6) Now DATA which needs to write will be sent by master in a packet of 8 bit. After reception of each packet slave will send ACK.
7) STOP: Once data transmission is over master will generate it by transmitting SDA from LOW to HIGH when SCL is HIGH.
8) If I2C wants to perform READ operation then also it will first go for WRITE operation and once register is selected, after generating repeated START it will go into READ operation. For that 8th bit of first data byte will be one.
9) Master will send slave address for read operation to the slave.
10) Master will receive data from slave and acknowledges the slave.
11) Master will generate STOP condition for termination.
Fig: I2C Byte Command Finite Machine.
The Verilog coding is synthesized in Xilinx ISE 13.2i and simulated in ModelSim 6.4a. the reports and simulation parameters are as follows:
Fig: I2C Master with READ enable.
Fig: I2C Master with WRITE enable.
Fig: I2C Master with Wishbone signal and slave operation.
FAMILY SPEED GRADE UTILIZATION
SPARTAN 3A -6 201 >50 33
SPARTAN 3A -4 201 >50 33
SPARTAN 3A -3 198 >50 33
AUTOMOTIVE 9500 XL -6 203 >50 33
LatticeECP3' -6 261 >50 33
LatticeXP2' -5 252 >50 33
From the above observations it is clear that, compare to other families SPARTAN 3A with speed grade -3 is utilizing the less number of LUT's.
I2C multi master controller with wishbone interface is designed and implemented, and this combination will enhance the performance of the design due to Multi number of masters and slaves that are connect to the wishbone interface. The wishbone interface is a powerful media that will allow full duplex communication with only two signals and control each device connected to it, making the design efficient. Also we can extend the same with the Spartan3 FPGA for knowing the worst path timing delay and its power constraints.
. Philips Semiconductor 'I2C Bus Specification' version 2 1, January 2000.
. R.W.Apperson, et al., "A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains", IEEE Trans. VLSI Systems, vol. 15, no. 10, pp. 1125-1133, Oct. 2007.
. "Open Core Protocol Specification", OCP-IP Association, 2001.
. Shen-Fu Hsiao, Chi-Guang Lin, Po-Han Wu and Chia-Sheng Wen, "Asynchronous AHB Bus Interface Designs in a Multiple-Clock-Domain Graphics System", IEEE, 2012.
. P.Venkateswaran, A. Saynal, S. Das, S.K Saynal and R. Nandi , "FPGA Based Efficient Interface Model for Scale-Free Computer Networking using I2C Protocol", 15th international conference on computing- CIC 2006, proc. Research in computer science: special issue ' advances in computer science &eng., ISSN 1870-406, pub. National polytechnic institute, Mexico, vol. 23, pp 191-198, Nov. 21-24, 2006.
. Vincent Himpe, 'Mastering the I2C bus' Elektor Verlag publications, 2011.
. Raj kamal ,'Embedded system: Architecture programming and Design',Tata McGraw Hill,2008.
G.Nandini persuing M.Tech degree in Digital Electronics and Communication Systems (DECS) from NBKRIST, Vidyanagar. Received B.Tech Degree in Electronics and Communication Engineering from Gokula Krishna College of Engineering, Sullurpet in 2014.
Dr.K.Nagi Reddy working as Professor in NBKRIST, Vidyanagar. He obtained his doctoral degree in the field of Signal Processing from S.V University, Tirupati. Received M.Tech degree in Digital Electronics and Communication Systems (DECS) from JNTU Hyderabad and B.Tech degree in Electronics and Communication Engineering from AMIETE.
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