Essay: Gate Diffusion Input Technique(GDI).

Abstract’ The paper presents to design of 8-bit Arithmetic and Logic Unit and bi-directional shift register by taking the advantage of concept called Gate Diffusion Input Technique(GDI).The bi-directional shift register is designed by using the D-Flip Flop with the concept GDI technique. D-flip flop is a one bit storage element to store a one bit data. To design D-flip flop NAND gates are required. Arithmetic and Logic Unit is the important block to design the embedded and microprocessors. The Arithmetic Unit will do the arithmetic operations, as ADDITION and SUBSTRACTION. The Logic unit will do the logic operations, as AND, OR, XOR and XNOR by using the concept GDI technique. The simulation results were taken using the Digital Schematic tool in 120nm technology. The optimized Area and Power is calculated by using Micro Wind tool in 120 nm technology. The simulation results tells that the design is more efficient compared with the CMOS logic, Pass transistor logic and transmission gate logic with less area and power consumption.
Keywords ‘ GDI technique, ALU, Bidirectional Shift register, CMOS, Pass Transistor Logic
I. INTRODUCTION
The Arithmetic Logic Unit and Bi-directional shift registers are designed with less area and less power consumption and less propagation delay by reducing the number of transistors count by using the concept called GDI technique. The Arithmetic and Logic Unit are used in high speed low power application design processors. The bi-directional shift registers is
a type of sequential logic circuits to store a digital data. The flip flop used to design bi-directional shift register is D-flip flop. Group of D-flip flops connected in the form of chain so that the output from one D-flip flop becomes the input to the next stage of the D-flip flop. In shift register the data allows each of the flip flops to pass the stored information to the adjacent neighbor.
Section II explains about the previous works. Section III explains Gate Diffusion Input technique. Section IV contains Arithmetic and Logic unit operation. Section V describes about the D-Flip Flop and Bi-directional shift register. Section VI analyses about the simulation results and Section VII gives you the conclusion.
II. PREVIOUS WORKS
One bit full adder is main building block to design the 4-bit ALU. To design one bit full adder there are different design techniques involved. Conventional CMOS, CPL, TFA, TG CMOS, C2MOS, Hybrid, Bridge, FA24T, N-cell, DPL and Mod2f are the twelve states of arts to design the full adder. The above design techniques requires the more number of transistors so that the area required to design will be more and takes high power consumption. The combination of NMOS transistor and a PMOS transistor forms a CMOS transistor. The number of transistors required to design CMOS full adder are 28 (no’s). The figure 1 shows Schematic diagram of CMOS adder which consists of 28 transistors. The number of transistors required to design full adder by using Transmission Gates technique is 14 numbers of transistors. The figure 2 shows a transmission gate full adder which is generated by using 14 transistors.
Figure 1 CMOS Full Adder Design
Figure 2 Full Adder Designed By using Transmission Gates
III. GATE DIFFUSION INPUT TECHNIQUE
Gate Diffusion Input Technique is a new technique to reduce propagation delay, area and power dissipation. The best method to design low power digital combinational circuits is GDI Technique. GDI technique is basically two transistor implementation of complex logic functions which provides in-cell swing restoration under certain operating conditions. The main feature of GDI cell is the VDD source will not connect to the source of PMOS transistor and the GND will not connect to the source of NMOS transistor. In the place of VDD and GND pins input signals are used to make more flexible than CMOS design. Figure 3 shows the Basic GDI cell. The figure explains that there are three inputs in a Basic GDI cell. G(common gate input to NMOS and PMOS), p(input to the source/drain of PMOS) and N(input to the source/drain of NMOS). Table 1 shows the different logic functions implemented with less power consumption and less propagation delay compared to other design techniques.
Figure 3 Basic GDI cell
Table 1 Logic functions of Basic GDI cell
The circuits required to design Arithmetic and Logic unit are A. Multiplexer
B. XOR Gate
C. Full Adder
Multiplexer will acts as a digital switch. Selection line plays a major role to select particular input. If the number of input lines is ‘2n’ and selection lines will be ‘n’ selection lines. With the ‘n’ selection line the particular ‘2n’ input line will be selected. Figure 4 shows the implementation of 2×1 multiplexer and Figure 5 shows the layout of 2×1 multiplexer. The number of selection lines for 2×1 multiplexer is one selection line. With respect to the select line the inputs will be selected. In the same way 4×1 multiplexer also designed to execute arithmetic and logic unit. The number of selection lines required for 4×1 multiplexer is two and with respect to the two selection lines the four inputs will be activated. Figure 6 shows the schematic of 4×1 multiplexer and figure 7 shows the layout of 4×1 multiplexer.
Figure 4 Schematic of GDI based 2×1 Multiplexer
Figure 5 Layout design of GDI based 2×1 Multiplexer
Figure 6 Schematic of GDI based 4×1 Multiplexer
Figure 7 Layout design of GDI based 4×1 Multiplexer
XOR gate is the main building block of the full adder and also which gives the sum output of the full adder. The number of transistors taken to design the XOR gate is four. So the adder circuit can be improved by reducing the area of XOR gate. Figure 8 shows the implementation of XOR gate and Figure 9 shows the layout design of the XOR gate.
Figure 8 Schematic of GDI based XOR gate
Figure 9 Layout design of GDI based XOR gate
One bit full adder circuit is also an important block to design Arithmetic and logic unit. Full adder circuit contains three inputs and two outputs named sum and carry. The operation adds only for one bit numbers. The number of transistors required to design one bit full adder are less so the area will be optimized for the better performance of arithmetic and logic unit circuit design. Figure 10 shows the implementation of the one bit full adder and Figure 11 shows the layout design of one bit full adder.
Figure 10 Schematic of GDI based one bit Full Adder
Figure 11 Layout design of GDI bases one bit Full Adder
IV ARTHMETIC AND LOGIC UNIT
Arithmetic and Logic unit is a important block of the central processing unit. Arithmetic unit performs arithmetic operations like Addition, Subtraction, increment and decrement operations. Logic unit performs logical operations like AND, OR, EXOR, EXNOR and SUM. In Arithmetic and logic unit Logic ‘0’ and Logic ‘1’ is applied as an input to the 4×1 multiplexer. Logic ‘0’ will result you the Decrement operation and Logic ‘1’ will result you the Increment operation. To design Arithmetic and Logic unit the required circuits are 2×1 multiplexer, 4×1 multiplexer, one bit full adder. Figure 12 shows the implementation of one bit Arithmetic and Logic unit and Figure 13 shows the layout design of one bit Arithmetic and Logic unit. In the figure 12 the 5bit adder is nothing but full adder which gives the six outputs are XOR, XNOR, AND, OR, SUM, CARRY. The four outputs of the full adder that is XOR, XNOR, AND and Or will give to the second 4×1 multiplexer shows in the figure 12.
Figure 12 Schematic of GDI based one bit ALU
Figure 13 Layout design of GDI based one bit ALU
In the same way the same way the second bit ALU is also shown. Figure 14 shows the implementation of second bit ALU and Figure 15 shows the layout design of second bit ALU. In second bit ALU the carry out of the first bit ALU will acts as an input to the Cin of the second bit ALU. Table 2 shows the operations of the Arithmetic and Logic unit.
Figure 14 Schematic of a GDI based second bit ALU
Figure 15 Layout design of a GDI based second bit ALU
By taking the Figure 12 and Figure 14 the 4-bit ALU is designed. To design the 4-bit ALU eight 4×1 multiplexers, four 2×1 multiplexers, four full adders are required. With respect to the selection inputs s0, s1 and s2 the ALU operations will be performed. The Table 2 shows the operations of the ALU. Figure 16 shows the implementation of the 4 bit ALU and Figure 17 shows the implementation of the Layout design of the GDI based 4 bit ALU
Table 2 ALU operations
Figure 16 Schematic of GDI based 4 bit ALU
Figure 17 Layout design of GDI based 4 bit ALU
Up to now we have seen the 4 bit ALU design and by taking the importance of the 4 bit ALU we design the 8 bit ALU design. In GDI technique by reducing the number of transistors in the full adder, 2×1 multiplexer and 4×1 multiplexer the ALU designed with less propagation delay, low power consumption and less area. Figure 18 shows the implementation of GDI based 8 bit ALU and Figure 19 shows the layout design of GDI based 8 bit ALU.
Figure 18 Schematic of GDI based 8 bit ALU
Figure 19 Layout design of GDI based 8 bit ALU
Table 3 shows the comparison analysis between Pass Transistor logic, CMOS Design and GDI Technique. Table 4 shows the comparison power analysis for 4-bit ALU and Table 5 shows the comparison power analysis for the 8 bit ALU.
Table 3 Comparison Analysis for ALU
Table 4 Analysis of Power for 4-bit ALU
Table 5 Analysis of Power for 8-bit ALU
V SIMULATION RESULTS
Figure 20 Simulation results for Function F1=A’B
Figure 21 Simulation results for Function F2=A’+B
Figure 22 Simulation results for GDI based AND gate
Figure 23 Simulation results for GDI based NOT gate
Figure 24 Simulation results for GDI based OR gate
Figure 25 Simulation results for 2×1 Multiplexer
Figure 26 Simulation results for 4×1 Multiplexer
Figure 27 Simulation results for GDI based XOR gate
Figure 28 Simulation results for GDI based Full Adder