Essay: Assignment: THE R-S FLIP FLOP CIRCUIT USING GATES R-S FLIP FLOP

LEARNING OBJECTIVE: VERIFICATION OF TRUTH TABLES OF FLIPFLOPS USING GATES
COMPONENTS REQUIRED
1. IC’s – 7410, 7400
2. Electronic circuit designer
3. Connecting patch chords
THEORY: The R-S (Reset Set) flip flop is the simplest flip flop of all and easiest to understand. It is basically a device which has two outputs one output being the inverse or complement of the other and two inputs. A pulse on one of the inputs to take on a particular logical state. The outputs will then remain in this state until a similar pulse is applied to the other input. The two inputs are called the Set and Reset input (sometimes called the preset and clear inputs). Such flip flop can be made simply by cross coupling two inverting gates either NAND or NOR gate could be used Figure shows on RS flip flop using NAND gate. the gate circuit and gate symbol of a NAND type clocked RS FF. The clock (CLK) determines the times at which the S and R input signals should be effective. A clocked RS FF is often provided with clear (CLR) and pre-set (PRE) terminals that allow the normal inputs to be overridden. These inputs are asynchronous to the rest of the circuit and cannot be both asserted at the same time.
Circuit Diagrams:-
Truth Table:
S R Qn Qn+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 x
1 1 1 x
Procedure:
1. Construct the SR Flip Flop.
2. Connect the Flip-flop circuits as shown above.
3. Apply different combinations of inputs and observe the outputs
4. Manually test all possible input combinations with clock C = 1 and record both the input and output voltages with a DMM.
5. Set the clock high, tie S and R together to the output of the function generator ‘sync out’ and set the frequency to 100 kHz. Observe the output on a DLA and note any irregularities.
Result: S-R Flip-flops using gates are constructed and its truth tables is verified
Precautions:
1. All the connections should be made properly.
2. Do NOT apply more than 5 V to the circuit at any time.
3. Arrange your circuit components neatly and in a logical order.
4. Turn off all power supplies any time that you make any change to the circuit.
VIVA QUESTIONS
1. List four Basic Flip-flop applications.
2. Explain the difference between a latch and a flip-flop?
3. Draw the circuit diagram of R-S flip flop using NOR gate?
PRACTICAL 7(B)
Aim: ‘ TO STUDY THE J-K FLIP FLOP CIRCUIT USING GATES
LEARNING OBJECTIVE: VERIFICATION OF TRUTH TABLES OF J-K FLIP FLOP USING GATES
COMPONENTS REQUIRED
1. IC’s – 7410, 7400
2. Electronic circuit designer
3. Connecting patch chords
THEORY: One of the most useful and versatile flip flop is the JK flip flop the unique features of a JK flip flop are that if the J and K input are both at 1 and the clock pulse is applied, then the output will change state, regardless of its previous condition and if both J and K inputs are at 0 and the clock pulse is applied there will be no change in the output. There is no indeterminate condition; in the operation of JK flip flop i.e. it has no ambiguous state. The circuit diagram for a JK flip flop is shown in figure
Circuit Diagrams:-
Truth Table:
J K Qn Qn+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Procedure:
6. Construct the J-K Flip Flop.
7. Connect the Flip-flop circuits as shown above.
8. Apply different combinations of inputs and observe the outputs
9. Manually test all possible (4) input combinations with clock C = 1 and record both the input and output voltages with a DMM.
10. Set the clock high, tie J and K together to the output of the function generator ‘sync out’ and set the frequency to 100 kHz. Observe the output on a DLA and note any irregularities.
Result: Different Flip-flops using gates are constructed and their truth tables are verified
Precautions:
5. All the connections should be made properly.
6. Do NOT apply more than 5 V to the circuit at any time.
7. Arrange your circuit components neatly and in a logical order.
8. Turn off all power supplies any time that you make any change to the circuit.
VIVA QUESTIONS
1. List four J-K Flip-flop applications?
2. Explain the difference between a S-R Flip Flop and J-K flip-flop?
3. Draw the circuit diagram of J-K flip flop using NOR gate?
PRACTICAL 7(C)
Aim: ‘ TO STUDY THE R-S FLIP FLOP CIRCUIT USING GATES MASTER SLAVE J-K FLIP FLOP
LEARNING OBJECTIVE: VERIFICATION OF TRUTH TABLES OF MASTER SLAVE J-K FLIP FLOP USING GATES
COMPONENTS REQUIRED
1. IC’s – 7410, 7400
2. Electronic circuit designer
3. Connecting patch chords
THEORY: The input signals J and K are connected to the gated ‘master’ SR flip flop which ‘locks’ the input condition while the clock (Clk) input is ‘HIGH’ at logic level ‘1’. As the clock input of the ‘slave’ flip flop is the inverse (complement) of the ‘master’ clock input, the ‘slave’ SR flip flop does not toggle. The outputs from the ‘master’ flip flop are only ‘seen’ by the gated ‘slave’ flip flop when the clock input goes ‘LOW’ to logic level ‘0’.
When the clock is ‘LOW’, the outputs from the ‘master’ flip flop are latched and any additional changes to its inputs are ignored. The gated ‘slave’ flip flop now responds to the state of its inputs passed over by the ‘master’ section.
Then on the ‘Low-to-High’ transition of the clock pulse the inputs of the ‘master’ flip flop are fed through to the gated inputs of the ‘slave’ flip flop and on the ‘High-to-Low’ transition the same inputs are reflected on the output of the ‘slave’ making this type of flip flop edge or pulse-triggered.
Then, the circuit accepts input data when the clock signal is ‘HIGH’, and passes the data to the output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip flop is a ‘Synchronous’ device as it only passes data with the timing of the clock signal
Circuit Diagrams:-
Truth Table:
J K Qn Qn+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Procedure:
11. Construct the Master-Slave JK Flip.
12. Connect the Flip-flop circuits as shown above.
13. Apply different combinations of inputs and observe the outputs
14. Manually test all possible (4) input combinations with clock C = 1 and record both the input and output voltages with a DMM.
15. Set the clock high, tie J and K together to the output of the function generator ‘sync out’ and set the frequency to 100 kHz. Observe the output on a DLA and note any irregularities.
Result: Different Flip-flops using gates are constructed and their truth tables are verified
Precautions:
9. All the connections should be made properly.
10. Do NOT apply more than 5 V to the circuit at any time.
11. Arrange your circuit components neatly and in a logical order.
12. Turn off all power supplies any time that you make any change to the circuit.
VIVA QUESTIONS
1. List four J-K Flip-flop applications?
2. Explain the difference between Master-Slave JK Flip and J-K flip-flop?
3. Explain Race around condition?
PRACTICAL 7(D)
Aim: ‘ TO STUDY THE R-S FLIP FLOP CIRCUIT USING GATES D-FLIP FLOP
LEARNING OBJECTIVE: VERIFICATION OF TRUTH TABLES OF D-FLIP FLOP USING GATES
COMPONENTS REQUIRED
1. IC’s – 7410, 7400
2. Electronic circuit designer
3. Connecting patch chords
THEORY: As the name implies the purpose of a D FF is to temporary store (or delay) a single bit. A signal of 0 or 1 present at the input D is transferred to the output Q whenever the clock CLK is set to 1. Fig. 1.3.1 shows the gate symbol of a D flip-flop. If we look closely at the truth table (Table 1.2.1) again we will see that it is quite simple to construct a D FF out of a JK FF. A delay flip-flop uses only the situations where the J and K inputs are different. This would make a D FF truth table only 2 lines. So how can we get rid of the other two lines in a JK FF truth table? We make sure they do not occur by connecting a NOT gate between the inputs J and K, as shown in Fig. 1.3.2. This way J and K will always be different.
Circuit Diagrams:-
Truth Table:
Clock D Qn Qn+1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
Procedure:
16. Construct the D Flip Flop.
17. Connect the Flip-flop circuits as shown above.
18. Apply different combinations of inputs and observe the outputs
19. Manually test all possible (4) input combinations with clock C = 1 and record both the input and output voltages with a DMM.
20. Set the clock high, D FF to the output of the function generator ‘sync out’ and set the frequency to 100 kHz. Observe the output on a DLA and note any irregularities.
Result: Different Flip-flops using gates are constructed and their truth tables are verified
Precautions:
13. All the connections should be made properly.
14. Do NOT apply more than 5 V to the circuit at any time.
15. Arrange your circuit components neatly and in a logical order.
16. Turn off all power supplies any time that you make any change to the circuit.
VIVA QUESTIONS
1. List four D FF applications?
2. Explain the difference between a D FF and J-K flip-flop?
3. Draw the circuit diagram of D FF using NOR gate?
n here…