Essay: 'Automatic Power Factor Control (APFC) based on PLC'

This report is about one type of control panel which is ‘Automatic Power Factor Control (APFC) based on PLC’. In our vast power system inductive loads are more. Therefore power factor is usually lagging in nature. This results in large current which inturn increases the machine size & losses, reduces efficiency and also has many more disadvantages. So all these problems are overcome by this panel.
Some key features of APFC are:
‘ Power factor is automatically controlled by APFC panel as per rules of government and also our requirement.
‘ One can reduce losses to enhance efficiency.
‘ Machine size and ratings are reduced.
In APFC, we can automatically compensate the effect of lagging load with the help of capacitor bank. This panel can be used in industry for correction of power factor.
The content of this report is a summary of what we have learnt and applied in the previous 5 months during the working and documentation of this project. It contains the complete study and analysis of the proposed system.
The present invention provides a system for correcting the power factor of small power installations, such as residences, apartments, small businesses, and the like. The system of the present invention generally includes a plurality of reactance units or capacitors which are selectively coupled to a power line and a sensor unit to determine if the capacitors connected to the power line have favorably affected the power factor.
In general, the present invention measures an electrical parameter of the power drawn by a load of a power installation which is capable of indicating a level of reactive power drawn by the load and couples a combination of reactance elements to the power line to substantially compensate for the level of reactive power indicated by the electrical parameter measured. The invention is directed to a first embodiment which is based entirely on a level of current measured and the effect of compensating reactance on the measured current level and a second embodiment which is based on a measurement of phase angle of the power drawn.
More particularly, the first embodiment of the power factor correction system of the present invention continually measures the current level drawn by the installation. When an increase in current is detected, it is assumed that a power load has been activated. A capacitor unit is connected to the power line, and the current measured again. If the current level increases, it is determined that capacitor unit has not favorably affected the power factor, and the capacitor is disconnected. If, on the other hand, connecting the capacitor caused the measured current to decrease, additional capacitance is connected to the power line. The process repeats until the current again rises, at which point, the most recently connected capacitor is disconnected.
In measuring the current drawn by loads within the power installation, the present invention averages a number of current measurements over time and takes no compensation action unless a change of a selected current difference is measured in less than a selected interval ov time. This approach, thus, reduces switching transients by making the system relatively immune to small variations in drawn current. In a preferred embodiment, the present invention bases compensating capacitance increments in multiples of a base capacitance which would result in a reactance that would draw about one ampere of current at the nominal power line frequency and voltage. The base capacitance is 22 microfarads for a power installation with a line frequency of 60 hertz and a nominal voltage of 110 volts.
The present invention maximizes the speed of arriving at a compensating combination of capacitors by providing a set of capacitors with values varying in powers of two multiplied by the base capacitance. The set of capacitors include: 1, 2, 4, 8 . . . 128 times the base capacitance. By this means, the power factor correction quickly arrives at an initial correction by doubling the value of compensating capacitance until the measured current level increases. In binary terms, this initial correction represents a ‘most significant digit’. The process continues, by incrementing rather than doubling, until an optimum combination is determined, which also fills in the ‘less significant digits’. A typical installation of the present invention includes a set of eight compensating capacitors with values ranging in powers of two from 1 to 128 times the base capacitance of 22 microfarads. The compensating capacitors are connected through latching switches across the power line. The latching switches are interfaced to an eight-bit output port of a controller, such as a microprocessor or microcontroller. By this means, the controller can connect any one of 256 combinations of the capacitors across the power line or disconnect any or all of the capacitors from the power line by writing an appropriate binary word to the output port in which the bit content of the binary word corresponds to the combination of capacitors to be connected or disconnected.
In the second, phase based, embodiment of the present invention, both current and voltage and the phase relationship there between are continually measured. The amount of compensating capacitance value to reduce the phase angle to near zero is calculated. Then a combination of capacitors which roughly equals the compensating capacitance value is coupled to the power line to compensate for the sensed inductive loads. The second embodiment of the present invention employs the same set of capacitors and, in general, the same apparatus as the first embodiment. Thus, the second embodiment uses a set of capacitors whose capacitance values are multiples of a base capacitance which would result in a reactance that would draw one ampere of current at the nominal line frequency and voltage. The set of capacitors also vary in value in powers of two multiplied by the base capacitance.