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Essay: Phase-locked loops (PLLs) for application-specific integrated circuits (ASICs)

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  • Subject area(s): Engineering essays
  • Reading time: 2 minutes
  • Price: Free download
  • Published: 5 December 2015*
  • File format: Text
  • Words: 335 (approx)
  • Number of pages: 2 (approx)

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One challenge in designing phase-locked loops (PLLs) for application-specific integrated circuits (ASICs) is providing ample flexibility for a wide variety of applications, including processors and video/chip interfaces. PLLs commonly are used to take low-frequency off-chip clocks, typically from crystals, and generate high-frequency on-chip clocks. The diversity of ASIC applications has also led to diversity in operating frequencies and multiplication factors required from PLLs.
For each PLL output frequency and multiplication factor, the loop parameters must be adjusted to minimize jitter and to guarantee stability. There are two jitter parameters of interest. One is long-term jitter, which is the deviation over time in the output clock edge time locations from those of an ideal clock output that is perfectly periodic. The other is period jitter, which is the variation over time in the period of the output clock. For a clock generator PLL, the output clock should track the input clocks as close as possible to minimize long-term jitter. It is also important to minimize the amount of period jitter.
These objectives pose a set of requirements on the loop parameters of the PLL. The loop bandwidth, which describes the response rate of the PLL, should be about 1/20 of the reference frequency. The damping factor, which describes the stability, should be about one. The third-order pole, which helps minimize period jitter, should be set at about 1/2 of the reference frequency. All of these loop parameters depend on specific circuit parameters, such as the charge pump current and the loop filter resistance. Thus, these parameters must vary with output frequency and multiplication factor. The diverse values of output frequency and multiplication factor can be addressed by designing a different PLL for each ASIC. This strategy makes it easier to meet constrained target specifications with less challenging circuits, but verifying all the designs in silicon for the ASICs that a company plans to build would be time consuming and costly. A better strategy is to create a single PLL design that can be ur text in here…

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