Essay: TCAM

A TCAM has three major components
(a) 8T BCAM cell that contains the stored data implemented using the cross coupled inverter and compare unit is implemented using pass transistor logic which compares the stored data with search data. Depending on the different applications, the compare unit can be implemented as XOR or XNOR functions.
(b) 6T SRAM cell is used for storing mask bit to indicate whether TCAM is in don’t care state or not. This is called Mask bit cell. TCAM state is determined by Mask bit (Mi). If Mi = 0, TCAM cell is in don’t care state in which there is always match regardless of the comparison result. Such condition is called Wild Match. If Mi = 1, in case of search data and stored data are identical it is called Normal Match otherwise it is Mismatch Condition.
(c) Evaluation logic is used to either pull down the ML or not. If the condition is Match then it retains the ML to logic high otherwise it is pull down to ground.
TCAM has three basic operations: write, read and compare operations. The NMOS access transistors and BLs which are used to read and write the SRAM storage bit. The SLs are used to broadcast search data and MLs are used to indicate the Match or Mismatch condition. BLs is used for performing read and writes operations.
Fig. 2(a) depicts NOR-type TCAM cell which usually implements XOR-type CAM cell and the pull down transistors of TCAM cell are arranged in NOR-type. During compare operation of TCAM in pre-charge phase, the ML is initially pre-charged to high. Transistors m3 and m4 are connected in series to indicate NOR-type cell, the status of ML is determined by the value of all four NMOS transistors m, m2, m3 and m4. In evaluation phase, if Mi = 0 ML remains in logic high state otherwise ML will be discharged to ground if output is in Mismatch State. The pull down path is very short, in case of a mismatch the ML is discharged to ground quickly compared to NAND-type TCAM hence it provides best compare performance. But at the cost of high power consumption as more power is dissipated in ML switching contributed by drain capacitances to ML.
Fig. 2(b) depicts NAND-type TCAM cell which usually implements XNOR-type CAM cell and the pull down transistors of TCAM cell are arranged in NAND-type. The ML is initially pre-charged to logic high, and discharged to 0 only when all CAM cells are matched. Because the load capacitance of ML is small and only one ML is discharged to 0 during search, hence the power consumption is minimal. As the pull down path is too long, such that the ML discharge is very slow in case of a Match. Thus, NAND-type TCAM consumes low power at cost of low performace.
Fig. 3 depicts Hybrid-type TCAM cell which achieves the best performance with low power consumption. When CAM performs compare operation, all the NAND MLs are activated. But only the NOR MLs with the corresponding NAND MLs generating a Match result are activated. Since the switching power of the NAND ML is less and only a small amount of NOR MLs are activated, the compare power of the CAM with NAND-NOR ML is better than that of the NAND ML. As shown in the fig. 3 the CAM cell is implemented as XNOR-type and their pull-down transistors are arranged in the NAND-type. The NAND-type block is connected to the ground only when all the CAM cells are matched. The XOR-type CAM cell is implemented and their pull down transistors are placed as NOR-type. The NOR-type block is disconnected from the ground only when all the CAM cells are matched.
During pre-charge phase, all the MLs are initially pre-charged to logic high and during the evaluation phase only those MLs which will be in mismatch state are pull down to ground.
(a) Pre-charge Phase: In this phase, the control signal Pre will be low. Thus ML is initially pre-charged to high. Because the pull down path T1, T2 and T3 are disconnected by N1, N2 and N3 transistors respectively both M1 and M2 nodes are pre-charged to high via P1 and P2. Due to no paths to the ground, it is unnecessary to discharge all the BLs to ground to prevent the unexpected short circuit during the pre-charge phase.
(b) Evaluation Phase: In this phase, the control signal Pre is asserted high and the search data have to be loaded on the BLs to start the matching process. This is called match evaluation phase. When both NAND-NOR type blocks are matched it is called normal Match. If the case is mismatch in NAND-type block then one of the NMOS transistor is turned off that disconnects the pull down path T1 from the ground. Therefore, node M1 retains high that turns off the tail transistor N2 and N3 to disconnect the pull down path T2 and T3 irrespective of the condition in NOR-type block node M2 will be still high to turn on N4. Because the path T1 and T2 are disconnected from the ground, the ML would retain logic high as in the initial phase. In case of Match in NAND-type block and Mismatch in NOR-type block, then NMOS transistors of NAND-type block are turned on that connects the path T1 to ground. Therefore, node M1 is discharged to ground that turns on the tail transistors N2 and N3.