Abstract’ This paper represents the method for
evaluating the reference current for the Distribution Static
Compensator (DSTATCOM) using power balance control
technique under static and dynamic conditions. In this
paper, three phase three wire VSC (Voltage Source
Converter) based DSTATCOM is used for power factor
correction, voltage regulation at point of common
coupling, load balancing of non linear load. The proposed
algorithm is simulated in MATLAB environment using
SIMULINK and Sim-Power System (SPS) toolbox. A
hardware prototype of DSTATCOM using dSPACE-1104
has been developed and test results are also presented for
unity power operation, harmonic compensation and load
balancing.
Keywords’DSTATCOM; unit templates; power quality;
DC link voltage; PI controller; harmonic compenstaion;
load balancing etc.
I. INTRODUCTION
The power quality issue [1] has become very prominent due
to proliferation of power electronic equipment. These
equipment cause various power quality problems on both
utility and customer side. In recent years, there is a great
emphasis on use of more automated and modern equipments
which are electronically controlled and energy efficient. These
equipment are also more sensitive to deviation in power supply
and power quality problems. The non-linear loads draw non
linear current and degrade electric power quality and this leads
to low power factor, low efficiency, overheating of
transformer, malfunction of sensitive devices, voltage sag and
swell, current harmonics, voltage harmonics, flicker, poor
power factor, increase losses, power interruption, reduced
overall efficiency [2].
To overcome these power quality issues, earlier passive
filters [3-4] were used to reduce the harmonics and improve the
power factor. But passive filters have limitations of fixed
compensation, large size and resonance. The increase severity
of harmonics lead to development of dynamic and adjustable
solution for power quality solution such equipments are called
active filters [5]. Distribution static compensator [6] is the
shunt connected active power filter which injects the current at
the point of common coupling. Figure 1 shows the system
configuration and design. For proper operation of
DSTATCOM, it is necessary to maintain dc link voltage at a
value such that pulse width modulation (PWM) control is not
lost.
Various control algorithms have been reported in the
literature such has p-q theory [7-8], synchronous d-q reference
frame method [9], neural network algorithm [10] to extract the
reference current of the compensator. Most of these methods
require various transformations and are difficult to implement.
In this paper, power balance control technique is used to extract
the reference source current for indirect current control and it
controls the DSTATCOM for power factor correction (PFC)
mode and zero voltage regulation (ZVR) mode along with the
load balancing and harmonic elimination. The model is
simulated in MATLAB environment using SIMULINK and
Sim Power System(SPS). The proposed control algorithm has
been implemented using dSPACE-1104 on developed
hardware prototype of DSTATCOM for load compensation.
II. SYSTEM CONFIGURATION
The basic block diagram of distribution static compensator
is shown in Figure 1. The distributed energy source is used as a
DSTATCOM comprising three leg voltage source converter
along with dc capacitor to provide an effective current control.
Three phase VSC is realized using six IGBT (insulated gate
bipolar transistor) switch with anti parallel diodes. A hysteresis
carrier less PWM current control [12] is employed for
generating switching signals. The three phase load is consists
of reactive load or unbalanced load or non linear load. The non
linear load is a three phase diode rectifier and resistance in
series with the inductor at the output terminal. An interfacing
inductor is used at the ac side to reduce the ripples in the
compensator current. RC filter is connected to the system to
reduce the switching ripples in the PCC voltage injected by
switching of DSTATCOM. The DSTATCOM is operated to
compensation of non-linear load, unbalanced load to correct
the power factor at the source side or to regulate the PCC
voltage. The power balance control algorithm is implemented
on developed hardware prototype of distribution static
compensator using dSPACE-1104 for load compensation.
III. CONTROL ALGORITHM
The control algorithm used for distribution static
compensator is based on power balance theory is shown in
Figure 2. The reference currents are extracted by sensing the
load current (ila, ilb, ilc), load voltage (vla, vlb, vlc), source voltage
(vsa, vsb, vsc), source current (isa, isb, isc), dc link voltage (Vdc),
voltage at PCC (Vtm) through current sensors and voltage
sensors.
The amplitude of PCC voltage is calculated from equation 1.
Vtm =
( v + v
+ v ) (1)
Where, vta, vtb and vtc are terminal voltages at point of common
coupling.
Unit vector templates in phase with PCC voltage are
obtained from the equation 2.
ua =
; ub =
; uc =
(2)
Unit vectors in quadrature with the PCC voltage are
obtained from the equation 3.
wa = (uc – ub)/3
wb = ua/ 2 + (ub – uc)/ 6 (3)
wc = (ub – uc)/6 ‘ ua/2
The instantaneous active and reactive power is calculated
from equation 4.
pload = Vtm??(ua iLa+ ub iLb+uc iLc)
qload = Vtm??(wa iLa+ wb iLb+wc iLc) (4)
Total calculated power is filtered through low pass filter to
extract the DC component.
pload = +
qload = +
For obtaining the power factor correction, it is assumed that
source supplies the load active power (pload) and power loss
(ploss) in the converter. The reactive power requirement of the
load is fed locally from distribution static compensator. The
DC component () of load active power is extracted by
filtering it through low pass filter from which required active
load current (Isd) is calculated as shown in equation 5.
For the regulation of DC link bus voltage (Vdc), a PI
controller is employed. The output of this PI controller is
considered as loss component of power in the converter is
shown in equation 6.
Where, Vde(n) = Vdcr ‘ Vdc(n) denotes the error between sensed
DC voltage and reference DC voltage. kpd and kid are
proportional and integral gains of DC bus voltage PI
controller.
The amplitude of active power component of the reference
source current is calculated from equation 7.
For zero voltage regulation, another PI controller is
employed over the amplitude of AC terminal voltage at point
of common coupling. The AC terminal voltage is filtered
through low pass filter to obtain DC component. The output of
this PI controller is shown in the equation 8.
iloss(n) = iloss(n-1)+kpd {Vde ‘ Vde(n-1)}+ kid Vde(n) (6)
Isd =
??
(5)
isdr = Isd + iloss
isdar = ua ?? isdr
isdbr = ub ?? isdr (7)
isdcr = uc ?? isdr
iacq(n) = iacq(n-1) +kpq {Vae ‘ Vae(n-1)}+ kiq Vae(n) (8)
Figure 1. System configuration.
Figure 2. Block diagram of control algorithm.
Where, Vae(n) = Vtmr ‘ Vtm(n) denotes the error between sensed
AC voltage and reference AC voltage at point of common
coupling. kpq and kiq are proportional and integral gains of AC
voltage PI controller.
The amplitude of reactive load current Isq is calculated from
equation 9.
The reactive power component of the source current are
calculated as
isqr = iacq + Isq
isqar = wa ?? isqr
isqbr = wb ?? isqr (10)
isqcr = wc ?? isqr
The total reference currents for all the three phases are
obtained by respectively adding the d and q components are
shown in equation 11.
Isar = isdar + isqar
Isbr = isdbr + isqbr (11)
Iscr = isdcr + isqcr
Thus the reference current generated is compared with the
sensed actual source current and is fed through hysteresis
Isq =
??
(9)
Figure 4. Performance of DSTATCOM in ZVR mode for non-linear load under balance/unbalance condition.
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55
-100
0
100
vabc
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55
-10
0
10
isabc
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55
-10
0
10
icabc
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55
-5
0
5
ilabc
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55
180
200
220
Vdc
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55
80
90
Time
Vtm
Figure 3. Performance of DSTATCOM in PFC mode for non-linear load under balance /unbalance condition.
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55
-100
0
100
v a b c
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55
-10
0
10
is a b c
-5
0
5
ic a b c
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55
-5
0
5
i la b c
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55
180
200
220
V d c
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55
80
90
Time
V tm
current controller to generate switching signals for
DSTATCOM.
IV. MATLAB BASED MODEL
A model of distribution static compensator and its controller is
developed in MATLAB environment using SIMULINK and
Sim Power System (SPS) toolboxes is shown in Figure 5.
V. SIMULATION RESULTS
The performance of distribution static compensator is
evaluated in MATLAB environment using SIMULINK and
SPS toolboxes. The DC voltage of DSTATCOM is selected
200V for the source voltage of 110V. For self supporting DC
bus voltage of DSTATCOM, a capacitor of 1640??F is used.
The VSC is connected through 3.4mH inductor to the network.
A non linear load is a three phase diode rectifier with
resistance of 35 and inductor 100mH in series. The
simulation results are taken for both power factor correction
(PFC) and zero voltage regulation (ZVR) for the same load
conditions. The results are obtained for two different cases.
Case(a) Performance of DSTATCOM in PFC mode
Figure 3 shows the performance of DSTATCOM under steady
state and dynamic condition for power factor correction,
harmonic reduction and load balancing. The simulation result
shows that DC link voltage reaches it steady state value at
t=0.06s and remains in steady state till t=0.2s. In the non linear
load, phase c and phase b are removed at t=0.2s and t=0.25s
respectively. It is observed that there is rise in DC link voltage
and it regain its steady state value within few cycles.
Similarly, phase c and phase b are added at t=0.3s and t=0.4s
respectively. It is observed that there is dip in DC link voltage
and it regain its steady state value within few cycle. The
source voltage (vsa, vsb, vsc), source current (isa, isb, isc),
compensator current (ica, icb, icc), load current (ila, ilb, ilc), DC
bus voltage (Vdc), PCC voltage (Vtm) are shown in figure 3. It
is observed that source currents are balanced, harmonic free
and in phase with PCC voltage irrespective of the balanced or
unbalanced load conditions as the loads are compensated by
DSTATCOM. The DC bus voltage is also regulated to its
reference value. Figure 6 shows the waveform THD and
harmonic spectra of source current and load current. The THD
of source current is 3.82% when load current THD is 28.15%.
Case(b) Performance of DSTATCOM in ZVR mode
The performance of DSTATCOM in ZVR is evaluated for the
same load conditions as in PFC mode. The results are shown
in Figure 4. It is observed that the PCC voltage regulates to
reference value under both balanced and unbalanced
conditions. DC voltage is also maintained to its reference
voltage by the controller. It is seen that non linear load is
compensated by DSTATCOM and make the source currents
harmonic free and balanced when the non linear load is
unbalanced. Figure 7 shows THD and harmonic spectra of
source current and load current. The THD of source current is
3.78% when the THD of load current is 28.15%.
(a)
(b)
Figure 6. THD waveform in PFC mode (a) THD of source current in
phase a. (b) THD of load current in phase a.
0.6 0.61 0.62 0.63 0.64 0.65 0.66
-10
-5
0
5
10
Time (s)
isa
0 2 4 6 8 10 12
0
20
40
60
80
100
120
Harmonic order
Fundamental (50Hz) = 4.651 , THD= 3.82%
Mag (% of Fundamental)
0.6 0.61 0.62 0.63 0.64 0.65 0.66
-10
-5
0
5
10
Time (s)
ila
0 2 4 6 8 10 12
0
20
40
60
80
100
120
Harmonic order
Fundament al (50Hz) = 4.659 , THD= 28.15%
Mag (% of Fundamental)
(a)
(b)
Figure 7. THD waveform in ZVR mode (a)THD of source current in
phase a. (b) THD of load current in phase a.
0.6 0.61 0.62 0.63 0.64 0.65 0.66
-10
-5
0
5
10
Time (s)
isa
0 2 4 6 8 10 12
0
20
40
60
80
100
120
Harmonic order
Fundamental (50Hz) = 5. 254 , THD= 3. 78%
Mag (% of Fundamental)
0.6 0.61 0.62 0.63 0.64 0.65 0.66
-10
-5
0
5
10
Time (s)
ila
0 2 4 6 8 10 12
0
20
40
60
80
100
120
Harmonic order
Fundamental (50Hz) = 4.659 , THD= 28.15%
Mag (% of Fundamental)
Figure 5. MATLAB model
VI. HARDWARE RESULTS
The system details for hardware implementation are
mentioned in the Appendix. The same parameters chosen for
simulation are considered for hardware implementation. A
prototype of DSTATCOM is developed using ‘Semikron’
three leg VSC with six IGBTs. Five current sensors (LEM
LA25) and four voltage sensors (LEM LV 25) are used for
sensing various current and voltage signals.
The proposed control model is implemented using dSPACE
1104 processor. The test results recorded using fluke 43B
power analyzer. The performance of DSTATCOM is tested
for different non-linear load conditions in PFC mode.
Figure 8 shows the waveform of source current, load current
and compensator current with DC link voltage under steady
state condition. Figure 9 shows the dynamic condition of
DSTATCOM in which load from phase ‘c’ is removed. The
load current in phase ‘c’ becomes zero. This results in sudden
increase in DC link voltage which settle down to its reference
value very quickly by controllers action. During phase
removal DSTATCOM supplies increased compensator current
to make supply current in phase ‘c’ sinusoidal and thus the
source current reduces slightly and remain balanced. In Figure
10 phase ‘c’ is added to remove unbalancing thus the ilc
increases. This results in sudden dip in the DC link voltage
which settle down to its reference value very quickly. This
causes reduction in compensator current and increase in
source current. The source current remains in balanced
condition. The non-linear loads current are compensated by
DSTATCOM to make the source current harmonic free and
balanced even though the non-linear load is unbalanced.
Figure 11(a) shows the source voltage and source current
waveform which are sinusoidal. Figure 11(b) shows the THD
of source current in phase ‘a’ which is 4.7%. The THD of load
current in phase ‘a’ is 23.9% which is shown in Figure 11(c).
The THD of PCC voltage is shown in Figure 11(d) which is
3.1%. These results show the effective performance of control
algorithm.
(a) (b)
(b) (d)
Figure 11. (a) waveform of source voltage and source current. (b) THD of
source current. (c) THD of load current (d) THD of source voltage.
Figure 10. Waveform of source current, load current, compensator current
and DC link voltage when load is added in phase ‘c’.
Figure 9. Waveform of source current, load current, compensator current
and DC link voltage when load is removed in phase ‘c’.
Figure 8. Steady state waveform of source current, load current,
compensator current and Vdc
VII. CONCLUSION
This paper discusses power balance theory for control
of distributed energy source used as a compensator.
The results are illustrated for non-linear load in both
steady state and dynamic load conditions. MATLAB
model is implemented in Sim Power System and
three phase reference supply currents are evaluated
using power balance theory. Prototype model is
developed using the same simulation parameters.
Simulation as well as hardware implemented results
show THD of less than 5% in the supply current with
non linear load currents. Extensive simulation and
hardware result have been shown which prove that
DSTATCOM can be controlled using power balance
control algorithm for mitigating various power
quality problems.
APPENDIX
Data for Simulation and Hardware Implementation
The simulation model and hardware prototype has
same parameters: AC line voltage is 110V; frequency
50 Hz; DC capacitor value is 1640??F; DC link
reference voltage 200V; interfacing inductor 3.4mH;
3 phase non-linear load (3 phase diode rectifier and
R=16 & L=100mH); kpd= 0.3, kid= 0.05, kpq= 0.011,
kiq= 0.0008; five current sensors (LEM LI 25); two
voltage sensors (LEM LV 25).
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