ABSTRACT
Now a days, power conservation and low power design are one of the most important factors to be considered during chip design. If the devices like mobile phone, personal music player and so on consume less power, the longer it can be run on batteries between two recharges. But the quest for low power design in the mobile device space is nothing new. There is another overarching reason why the low power design is becoming so important today is the increase of leakage current with the shrinkage of device geometry. The leakage current is the current that flows from the drain to source of a transistor whether it is on or off state. The several systems of different functionalities are integrated on single chip called SoC and each of these systems is called as intellectual property (IP). As the technology reduces and thus reducing the channel length of MOSFET, the supply voltages and the threshold voltages decrease. This causes the sub-threshold current to increase exponentially (approximately 10 times per technology node). For example, at 130 nanometers with supply voltage of 1.2 – 1.3V, leakage current represents 10-30% of the active power. At 70 nanometers with supply voltage of 0.9 – 1.0V, leakage current is 50% of the power dissipation of the chip. The common methodology adopted for reducing power at larger geometry is to shut the clock to a specific block that is not required to be operational at certain stage thus preventing the switching of the transistors. Since leakage current does not stop if the transistors stop switching, this method is ineffective at small geometry processes. The only way to stop the leakage current flowing through a transistor is by power down the supply voltage to that transistor. Another way of looking into this would be to power down the power supply to IP when its operation is non-essential to the overall chip. Power domain is the key concept behind solving the low power design and verification challenges. Each of these IP’s contains several power domains and power on or off depending on the requirement. Power management verification methodology checks for all the functionality of power domains. Verification is one of the most important factor in the process of Chip design. It is said that 70-80% of the complete ASIC Design flow is dedicated to chip verification. Earlier, it was not that big issue for verification as the number of transistors were less. But as the technology progresses, the complete system is built on chip called SoC. This SoC contains combination of Intellectual propertys (IP’s) and also each of the IPs contains now millions of transistor. So, the functional verification is performed to check the functionality of the device correctly by writing different test cases for the given IPs in verilog HDL.
OBJECTIVE AND PROBLEM DEFINITION
The main objective of the project is design and verification of APB-SPI interface using verilog HDL. This is to verify the functionality of IP. Also, it concentrates on low power design and verification of IPs using upf file in order to conserve the power.
LITERATURE SURVEY
Gate-level verification poses many issues such as low productivity, difficult debug, and elusive problem identification. Specifying power information directly into RTL code also has disadvantages. Directly instantiating retention registers and latches have a negative impact on the RTL coding style, and reuse as the RTL must be updated whenever the power strategy changes or new technology libraries are used, requiring modification of the RTL and corresponding re-verification of the blocks, a time consuming exercise. Thus, verification of power aware designs must begin at the RTL and should correlate the low power design intent to the RTL code.
The EDA industry began a quest for a single, standard low power format that would capture the low power design specification for use throughout the RTL to GDSII flow, and would apply consistent semantics for both verification and implementation. That is why Accellera developed the Unified Power Format (UPF), which presents the low power design intent in a portable and interoperable form that can be used with most design verification and implementation tools throughout the design flow. To preserve the integrity of the low power specification as it moves through the design and verification process, the UPF is written in TCL as a side file. This side file augments the HDL code to form a complete design specification at any level of abstraction. Because it is separate from the HDL description and can be read by all of the tools in the flow, the UPF side file is as portable and interoperable as the logic design’s HDL code.
UPF is a TCL-based specification format for low power designs. UPF specifies semantics for low power designs that are consistent between verification and implementation tools, making it possible to preserve the design intent throughout the design and verification flow. The low power design intent specifications of an IP or SoC can be captured in a UPF file, including Power networks, Power switches, Power domains, Retention logic, Isolation cells, Level shifters, and System power states. In addition to the specification of the low power design intent, UPF also defines semantics for Power in the OFF state and ON state.
Accellera and the UPF committee worked closely with IEEE and thus now all EDA industries have low power standard and roadmap through IEEE P1801 for further development.
POWER MANAGEMENT ARCHITECTURE AND BASIC PROTOCOLS OUTLINE
POWER MANAGEMENT STRATEGIES
The power management strategies includes Retention cells, Isolation cells and Level shifter. Basically, the entire chip is divided in different power domains based on functionality. Each of the power domains requires different voltage supply based on the usage of domain. It means the domains used frequently contains large VDD supply and vice versa. Also each of the domain gets switch-on and switch-off according to user requirement.
Level Shifter
Fig. 1
Level shifter is used when there is a large variation in supply voltages and threshold voltages of the two connected domains. Consider, Domain B and domain C in fig 1 which are working on different power supply voltages. It is assumed that logic 1 value for domain B and domain C is 0.9V and 3V respectively and logic 0 is 0V. From the observation, it is clear that threshold voltages for different domains will be different. In this case, it is assumed as 0.3V and 1.3 V for domain B and domain C respectively. If we observe carefully, it is found that logic 1 value for domain B is less than threshold value of domain C. So, when logic 1 value passes to domain C, it is wrongly taken as logic 0 as domain C will remain off and vice versa. So, in order to pass correct logic value between different domains, it is necessary to insert level shifter to increase or decrease the value based on the requirement.
Isolation Cell
It is used when power on domain is depend on power off domain values. When a power domain is shut off, any signal generated by that domain becomes logical X. This creates unique challenge to other domains that are not shut off at that time. As an example, let us consider the case when domain B is shut off while domain C is not. Of particular interest here is the signal S1 that runs from B to C. First, let us assume the case when S1 is not required in domain C when domain B is shut off. Even though it is not required, S1 will propagate X through C. There has to be some way to block X propagation of S1 in C. Isolation cell is used so that some stable value either logic 0 or logic 1 passes to domain C. This particular logic value is called clamp value and is set while writing the UPF commands. The clamp value can be set as 1 or 0.
Retention Cell
It is designed when we want to save the last generated values of power off domain and restore them again when domain gets into power on mode. As an example, consider the doamain B is shut off and domain C is on. Signal S1 which passes through domain B to domain C is required by domain C when domain B is off. Retention cell stores this signal value in temporary register and passes to domain C whenever it is required assuming that domain B is power off mode.
POWER AWARE SIMULATION FLOW
Fig.2 Simulation Flow
GENERAL DESCRIPTION OF SPI PROTOCOL
In a computer, a serial peripheral interface (SPI) is an interface that enables the serial (one bit at a time) exchange of data between two devices, one called a master and the other called a slave. An SPI operates in full duplex mode. This means that data can be transferred in both directions at the same time. The SPI is most often employed in systems for communication between the central processing unit (CPU) and peripheral devices. It is also possible to connect two microprocessors by means of SPI. The term was originally coined by Motorola. National Semiconductor has an equivalent interface called Microwire.
SPI Transmission Details
To begin a communication, the bus master first configures the clock, using a frequency less than or equal to the maximum frequency the slave device supports. Such frequencies are commonly in the range of 10kHz’100MHz. The master then transmits the logic 0 for the desired chip over the chip select line. A logic 0 is transmitted because the chip select line is active low, meaning it is off state is a logic 1 and on is asserted with a logic 0. If a waiting period is required (such as for analog-to-digital conversion), then the master must wait for at least that period of time before starting to issue clock cycles. During each SPI clock cycle, a full duplex data transmission occurs. The master sends a bit on the MOSI line; the slave reads it from that same line. The slave sends a bit on the MISO line; the master reads it from that same line.
Features of SPI protocol
‘ Full duplex synchronous serial data transfer
‘ Variable length of transfer word up to 128 bits
‘ MSB or LSB first data transfer
‘ Rx and Tx on both rising or falling edge of serial clock independently
‘ 8 slave select lines
‘ Fully static synchronous design with one clock domain
‘ Technology independent
GENERAL DESCRIPTION OF APB PROTOCOL
The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture (AMBA) hierarchy of buses and is optimized for minimal power consumption and reduced interface complexity. The AMBA APB should be used to interface to any peripherals which are low bandwidth and do not require the high performance of a pipelined bus interface.
Features of APB Protocol
‘ Performance is improved at high frequency operation.
‘ Performance is independent of mark-space ratio of the clock
‘ Static timing analysis is simplified by the use of single clock edge
‘ No special considerations required for automatic test insertion
‘ Easy integration with cycle based simulators
States of APB
The activity is performed on APB with the help of 3 states and state diagram is shown in figure below.
Fig.3 States of APB
‘ Idle state:
This is the default state of peripheral bus and it does not perform any operation.
‘ Setup state:
Whenever transfer is required, bus moves to this state from idle state. In this state, PSelx=1 and Penable=0. The address signal, write signal, write data signal is asserted at this state. The bus remains in this stage for one clock cycle and it always moves to enable state on the next rising edge of the signal.
‘ Enable state:
In this state, Penable=1 signal asserted. At this state, write or read operation is performed accordingly. The other signals such as address signal, write/ read signal remains stable during this state. Once the transfer is finished, it transits to idle state if no more operation is performed else it will get into loop of setup state and enable state.
SIGNAL DESCRIPTION FOR SPI AND APB
SIGNAL DESCRIPTION FOR SPI
Basically, SPI comprises of SPI master and SPI slave. The communication between master and slave is performed with the help of 4 basic signals as shown in figure below.
Fig4. Basic SPI Architecture
‘ SCLK: It is serial clock generated from master output and is the input to slaves. Slave operates on the edges of serial clock, not the global clock.
‘ MOSI: It is master out slave in signal.
‘ MISO: It is master in slave out.
‘ SS: It is slave select signal. SPI supports maximum 8 slaves. This signal selects one of the slaves to perform data transfer operation with master.
Internally, SPI master contains SPI clock generator, SPI shift register.
SPI master core basically consists of data transmit register, data receive register, control and status register, clock divider register and slave select register. All these registers are shown in table below.
Data receive registers(RxX)
Data receive registers are read only registers. SPI master core contains total of 4 receive registers each having 32 bit datawidth. It is read only register. It holds the received data of the last executed transfer. The number of bits received per transfer depends on the character field of control and status register of the SPI master core. If character field is less than 32 bit, only Rx0 is active and for 64 bits, Rx0 and Rx1 are active and so on. Data receive register is shown in table below.
Data transmit registers (TxX)
Data transmit registers are read/write registers. The number of bits transfer in given transfer depends on the character field of control and status register. If the character field is less than 32 bits, the Tx0 is used to transfer the data to SPI slave. If the character field is 64 bits, the TX0 and Tx1 is used and so on. Data transmit register is shown in table below.
Control and status register
As shown in table above, control register is 32 bit register and is important register in configuring SPI master.
‘ CHAR_LEN: It is 7 bit and indicates number bit transfer in a single transfer of SPI. Suppose, CHAR_LEN is set as 1 bit, 1 bit transfers in a single transfer. If it is 64 bits, 64 bits transfer in a single transfer. Likewise maximum of 128 bits are transferred using this character length field in control and status register.
‘ G0_BSY: This is go busy bit which indicates start of the data transfer in SPI. If this bit is set indicates start of transfer. The feature of this bit is that it gets automatically to zero once data transfer is finished indicating end of data transfer.
‘ Rx_NEG: This bit indicates receiption of the data transfer on the particular edge of serial clock cycle. If Rx_NEG=1, it shows data is received on the falling edge of serial clock SCLK else on the rising edge of SCLK.
‘ Tx_NEG: This bit indicates transmission of the data on the particular edge of SCLK. If Tx_NEG=1, it show that data is transmitted on the falling edge of clock cycle else on the rising edge of SCLK.
‘ LSB: This bit indicates mode of transfer i.e. either from LSB to MSB or MSB to LSB. If LSB=1, LSB is transmitted first otherwise MSB first.
‘ IE: If this bit is set, the interrupt output is set active after a transfer is finished. The interrupt signal is de-aaserted after read or write to any register.
‘ ASS: If this bit is set, slave is selected automatically. If this bit is cleared, slave is asserted and de-asserted by writing and clearing bits in SS register.
Divider register
This register indicates frequency of serial clock SCLK derived from global clock signal wb_clk_i. The desired frequency is obtained by
Fsclk = (fwb_clk) / (DIVIDER+1)*2
Slave select register
If CTRL[ASS] bit is cleared, writing a to any of the first 8 locations sets the corossponding slave.
In the given project, SPI is working along with APB through wishbone interface. Thus, we need to consider wishbone signal also as interface to SPI. All output wishbone signals are registered and driven on the rising edge of wb_clk_i. All input wishbone signals are latched on the rising edge of wb_clk_i.
Table below shows the list of wishbone interface signals.
DESCRIPTION OF UNIFIED POWER FORMAT COMMANDS
The Unified Power Format (UPF) provides the ability for electronic systems to be designed with power as a key consideration early in the process. UPF accomplishes this by allowing the specification of what was traditionally physical implementation-based power information early in the design process’at the register transfer level (RTL) or earlier. The figure 5 below shows the UPF supporting entire design flow.
A UPF specification defines how to create a supply network to supply power to each design element. Supply network consists of supply ports, supply nets, supply switches. Power domains are created based on switching of modules and each of the power domains contains several logic elements which share a common primary supply. By controlling the operating voltages of each supply net, the supply network only provides power at the level the functional areas of the chip need to complete the computational task in a timely manner. Supply net is the wire which provides supply to power domains. Supply ports provide the supply interface to the logical hierarchy and the power domain’s elements. Supply ports also provide the supply interface to switches. Switches control the supply distribution.
Fig.5 UPF tool flow
Thus according to user’s requirement, different power management strategies can be designed. These strategies are implemented using certain UPF commands as explained below. These commands are basically TCL commands and can be modified easily according to user’s requirement.
As per above discussion of architecture and power intent specifications, figure 6 shows the complete architecture for SPI module which contains separate power domains for top module, master module and slave module. The paper develops different strategies for controlling power of different IP’s in the given SoC. The given SoC contains APB-SPI interface through wishbone bridge. In this, APB module acts as a master and SPI module as a slave. The approach of the project developing .UPF file for both simple SPI and APB-SPI interface.
Fig.6 Power Architecture for SPI
1. create power domain:
create_power_domain pd_top
create_power_domain pd_master -elements {DUT1}
create_power_domain pd_slave -elements {DUT2}
create_power_domain pd_top is the command used to create top power domain. DUT1 and DUT2 are the design elements included in top power domain. A design element is member of power domain that includes design element’s parent instance.
2.create supply ports:
create_supply_port VDD_15 -domain pd_top
create_supply_port VDD_09 -domain pd_top
create_supply_port VSS -domain pd_top
create_supply_port is the command used to create ports for connecting supple nets to power supply. Here, seperate ports are defined like VDD_15 for master power domain which is 1.5V and VDD_09 for slave power domain i.e. 0.9V.
3. create supply nets:
create_supply_net VDD_15_n
-domain pd_top
create_supply_net VDD_09_n
-domain pd_top
create_supply_net VSS_n
-domain pd_top
create_supply_net is used to create supply nets for top domain for providing supply. As shown in command, it is seperately defined for corossponding power domains.
create_supply_net VDD_15_n
-domain pd_master -reuse
create_supply_net VSS_n
-domain pd_master -reuse
create_supply_net VDD_09_n
-domain pd_slave -reuse
create_supply_net VSS_n
-domain pd_slave -reuse
Also, separate nets are designed for each of the power domains included in top power domain. Actually same net is used as that of top power domain, it is declared as reuse.
4. connect supply nets:
connect_supply_net VDD_15_n
-ports VDD_15
connect_supply_net VDD_09_n
-ports VDD_09
connect_supply_net VSS_n
-ports VSS
connect_supply_net is used to connect given supply net to corresponding supply port. Here VDD_15_n indicates net name and VDD_15 indicates port name for master power domain. Similarly, VDD_09_n and VDD_09 indicates net name and port name for slave power domain respectively. VSS_n and VSS are the net name and port name for ground supply respectively and is effectively used for all the power domains.
5. create power switch for master and slave power domain:
create_power_switch master_sw
-output_supply_port
{vout_p master_pwr_n}
-input_supply_port
{vin_p VDD_15_n}
-control_port {cntrl_p spi_top_cntl}
-on_state {on_state vin_p {cntrl_p}}
-off_state {off_state {!cntrl_p}}
create_power_switch is command used to create power switch for master power domain. -control_port is used to declare control port and the conditions for switching on /off the supply is defined by -on_state and -off_state command respectively.
6. Define port states:
add_port_state VDD_15
-state {on_state 1.5}
-state {off_state off}
Port states define the actual supply provided to supply nets. on_state and off_state are the keyword representing the these supply values.
7. create and add power state table:
create_pst spi_pst -supplies {VDD_15 VDD_09 VSS master_sw/vout_p slave_sw/vout_p}
add_pst_state FULL_ON
-pst spi_pst
-state {on_state on_state on_state on_state on_state}
create_pst command is used to create different power states for different power supply mentioning list of supply nets in the command.
add_pst_state command specifies different states of power domains. It tells about which supply should be on and which should be off for corresponding power domains.
8. Define retention state and retention control:
set_retention master_ret
-domain pd_master
-retention_power_net VDD_15_n
-retention_ground_net VSS_n
set_retention_control master_ret
-domain pd_master
-save_signal {spi_top_save high}
-restore_signal {spi_top_restore low}
These commands define retention strategy for power domain. The signal is saved before domain gets switched off by command -save_signal and restore after domain is switched on by command -restore_signal.
9. Define isolation state and isolation control:
set_isolation master_iso
-domain pd_master
-isolation_power_net VDD_15_n
-isolation_ground_net VSS_n
-clamp_value 1
-applies_to outputs
-elements {DUT1}
set_isolation_control master_iso
-domain pd_master
-isolation_signal master_iso_c
-isolation_sense high
-location parent
These commands define isolation strategy for power domain.
10. Define level shifter and respective signals:
set_level_shifter ms_sl_in
-domain pd_master
-applies_to inputs
-location self
set_level_shifter ms_sl_out
-domain pd_master
-applies_to outputs
-location parent
In simple SPI protocol, it contains a master and a slave. SPI has a feature of full duplex communication i.e. transmitting and receiving simultaneously between master and slave. The strategy for developing power management is divided in three parts.
i. FULL OFF
In this power state, the entire top domain is off. When the device is off, there is no need to activate power strategies and thus it is used in idle state. Thus, power domain for master and slave are also in off state.
ii. PARTIAL ON
In this power state, power domain of master is on and that of slave is off. When SPI performs write operation through peripheral wishbone bridge, it writes data to MOSI (master out slave in) signal which acts as input to slave. Slave is required only at the time of read transfer in which we read the data through MISO (master in slave out) signal. Thus, there is possibility of conserving the power at the time of write transfer by switching off the power domain for slave.
iii. FULL ON
In this power state, power domain of master and slave are on. This state is used at the time of read transfer of SPI protocol. In this, whatever data is written to slave through MOSI signal is retrieved to master from MISO signal. Thus it is required to have both domains on simultaneously.
Thus, it can be observed that introducing .UPF file in test bench conserves the power of SPI protocol at the time of write transfer by switching off the slave module.
Similar results can be observed for APB-SPI interface by switching on and switching off the corresponding modules
SIMULATION RESULTS AND DISCUSSIONS
Fig.7 Simulation result for 8 bit serial data transfer
Fig.8 Simulation result for 8 bit data transfer showing master core control signals of UPF
Fig.9 Simulation result for 8 bit data transfer showing slave control signals of UPF
Fig.10 State machine representation of power off state
Fig.11 Schematic diagram representing of power off state
Fig.12 State machine representation of partial power on state
Fig.13 Schematic diagram representing partial power on state
Fig.14 State machine representation of full power on state
Fig.15 Schematic diagram representing full power on
According to the specifications, the given protocol is verified by writing different test cases. This can be done by configuring control and status register of SPI protocol. It is 32 bit register which decides the functionalities like number of bits transferred serially per cycle, whether MSB or LSB bit is transferred first. It also decides the edge for data transfer whether positive edge or negative edge by assigning the respective logic value to corresponding bit of register.
Based on this, the protocol is verified with and without instantiating UPF file in test cases and the waveforms shown below explained the results for the same.
Simulation result for 8 bit serial data transfer for SPI without considering the low power file is shown in figure 7. It indicates that master core register is configured when write enable is logic 1. This operation of writing data to master is performed in specific order and assigning the addresses and data to corresponding registers. The read operation is performed once write enable logic becomes 0 and data is transferred on the edges of SCLK.
The figure 8 and figure 9 indicates the data transfer considering low power file. It can be observed that power control switches defined in UPF file plays significant role in controlling power. Power control switch is on by assigning logic 1 value to control signal. As per the discussion of theory of isolation and retention cells, the retention signal should get on and isolation signal should be off when power control signal gets switched on. Also isolation signal should get switched on and retention signal should get switched off when the power control signal is off.
From figure 8, it is observed that during writing of the data to master, master core signals like spi_top_cntl and spi_top_restore are on and spi_top_save signal is off. Due to usage of power control signals during write transfer, MISO signal is switched off and thus helps in conserving power. This condition is shown in red line.
Also during read transfer , power domain for both master and slave are on. Thus, power control signals slave_cntl, slave_restore are on and slave_save is off. As per earlier discussion, during write power domain for slave is off and thus slave_cntl and slave_restore signals are off and slave_save signal is on as shown in figure 9.
Figure 10 represents the different states and conditions for the same in state table. It has been observed that power off state contains both master and slave power switch in off state represented. Figure 11 represents schematic diagram for both master and slave power domain. The off state of domains is highlighted by grey colour. Likewise partial power on condition is represented in figure 12 and figure 13. Also, full power on condition state diagram and schematic representation in figure 14 and figure 15.