We describe an experiment in using sensor-based data to identify individuals as they perform a simple activity of daily. (makingcoffee) The goal is to determine whether people have regular and recognizable patterns of interaction with objects as they perform such activities.We describe the use of a machine-learning algorithm to induce decision- trees that classify interaction patterns according to the subject who exhibited them; we consider which features of the sensor data have the
most effect on classification accuracy; and we consider ways of reducing the computational complexity introduced by the most important feature type. Although our experiment is preliminary, the results are encouraging: we are able to do identification with an overall accuracy rate of 97%, including correctly recognizing each individual in at least 9 of 10 trials.The system objective was to develop a computerized Indian Sign Language (ISL) recognition system. The system considers only single handed gestures; therefore a subset of ISL has been selected for
the implementation of Boltay Haath. The basic concept involves the use of computer interfaced data gloves worn by a disabled person who
makes the signs. The computer analyzes these gestures, minimizes the
variations and synthesizes the sound for the corresponding word or letter for normal people to understand. The basic working of the project is depicted in the following figure.The above diagram clearly explains the scope and use of the system. The system aims at bridging
communication gaps between the deaf community and other people. When fully operational the system will help in minimizing communication gaps, easier collaboration and will also enable sharing of ideas and experiences.The designed system input hand gestures to the system through an electronic sensor glove and it identifies the gesture patterns via microcontroller network. Then the identified
sign is converted to text and then translated to voice output. The basic working of the project is depicted in the following figure. The device supports both random and sequential access of multiple messages.
The above diagram clearly explains the scope and use of the system
Sample rates are user-selectable, allowing designers to customize their design for unique quality and storage time needs.Integrated output amplifier, microphone amplifier, and AGC circuits greatly simplify system design. the device is ideal for use in portable voice recorders, toys, and many other consumer and industrial applications. APLUS integrated achieves these high levels of storage capability by using its proprietary analog/multilevel storage technology implemented in an advanced Flash non-volatile memory process, where each memory cell can store 256 voltage levels.This technology enables the APR9600 device to reproduce voice signals in their natural form. It eliminates the need for encoding and compression, which often introduce distortion. The ADC0808, ADC0809 data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital converter, 8-channel multiplexer and microprocessor compatible control logic. The 8-bit A/D converter uses successive approximation as the conversion technique. The converter features a high impedance chopper stabilized comparator, a 256R voltage divider with analog switch tree and a successive approximation register. The 8-channel multiplexer can directly access any of 8-single-ended analog signals. The device eliminates the need for external zero and full-scale adjustments. Easy interfacing to microprocessors is provided by the latched and decoded multiplexer address inputs and latched TTL TRI-STATE outputs. The design of the ADC0808, ADC0809 has been optimized by incorporating the most desirable aspects of several A/D conversion techniques. The ADC0808, ADC0809 offers high speed, high accuracy, minimal temperature dependence, excellent long-term accuracy and repeatability, and consumes minimal power. These features make this device ideally suited to applications from process and machine control to consumer and automotive applications. For 16-channel multiplexer with common output (sample/hold port) see ADC0816 data sheet.
LIST OF FIGURES
Figure No.
Figure 2.1 Figure Description
System Diagram Page No.
02
Figure 2.2 Accelerometer MMA7260QT 03
Figure 2.3 Equivalent English symbols for Database 04
Figure 3.1 Block diagram of P89V51RD2 microcontroller 06
Figure 3.2 Pin Description of P89V51RD2 microcontroller 07
Figure 3.3 Main Board Schematic 12
Figure 3.4 Pin-out Diagram of APR9600 14
Figure 3.5 Block Diagram of APR9600 15
Figure 3.6 Application circuit of APR9600 17
Figure 4.1 MNA7260QT Accelerometer 18
Figure 4.2 Block Diagram of MNA7260QT Accelerometer 19
Figure 4.3
Figure 4.4 Sensing Axis for the MMA7260Q Accelerometer with
X, Y,And Z-Axis for Sensing Acceleration
Gravity Component of a title X-Axis Accelerometer 20
21
Figure 4.5 Gravity Component of a title Y-Axis Accelerometer 21
Figure 4.6 Schematic Accelerometer 22
Figure 5.1 Block Diagram of ADC0808/ADC0809 24
Figure 5.2 Connection Diagram of ADC0808/ADC0809 25
Figure 6.1 Flex sensors 27
Figure 6.2 Typical potentiometer 28
Figure 7.1 Functional Diagram 32
LIST OF TABLES
Table No. Table Description Page No.
Table 1 TMOD ‘ Timer/Counter mode control register bit allocation 10
Table 2 TMOD ‘ Timer/Counter mode control register bit allocation 10
Table 3 TMOD ‘ Timer/Counter mode control register M1/M0 11
Operating mode
Table 4
Table 5
TCON ‘ Timer/Counter mode control register bit allocation 11
TCON ‘ Timer/Counter mode control register bit description 11
Table 6 Maximum Ratings 19
Table 7
Table 8
Analog channel Selection 26
LCD Command code 31
Object Identification For deaf
Abstract:
The goal is to determine whether people have regular and recognizable patterns of interaction with objects as they perform such activities Our aim is to describe the design and working of a system which is useful for dumb, deaf and blind people to communication with one another and with the normal people. This system converts the sign language into voice which is easily understandable by blind and normal people. For that we will use microcontroller, ADC, Accelerometer, LCD display. The design of the ADC0808, ADC0809 has been optimized by incorporating the most desirable aspects of several A/D conversion techniques.
CHAPTER-1
INTRODUCTION
1.1 Aim
A System is developed to determined the object of deaf People. Speech and gestures are the expressions, which are mostly used in communication between human beings. Learning of their use begins with the first years of life. In human communication, the use of speech and gestures is completely coordinated. Machine gesture and sign language recognition is about recognition of gestures and sign language using gloves. A number of hardware techniques are used for gathering information about body positioning; typically either image-based (using cameras, moving lights etc) or device-based (using instrumented gloves, position trackers etc.), although hybrids are beginning to come about. However, getting the data is only the first step. The second step, that of recognizing the sign or gesture once it has been captured is much more challenging, especially in a continuous stream. In fact currently, this is the focus of the research.
The data is analyzed from an instrumented data glove for use in recognition
of some signs and gestures. A system is developed for recognizing these signs and their conversion into speech. The results will show that despite the noise and accuracy constraints of the equipment, the reasonable accuracy rates have been achieved. The basic concept involves the use of computer interfaced data gloves worn by a disabled person who makes the signs. The computer analyzes these gestures, minimizes the variations and synthesizes the sound for the corresponding word or letter for normal people to understand. A system is developed for recognizing these signs and their conversion into speech.
CHAPTER-2
SYSTEM OVERVIEW
The system objective was to develop a computerized Indian Sign Language (ISL) recognition system. The system considers only single handed gestures; therefore a subset of ISL has been selected for the implementation of Boltay Haath. The basic concept involves the use of computer interfaced data gloves worn by a disabled person who makes the signs. The computer analyzes these gestures, minimizes the variations and synthesizes the sound for the corresponding word or letter for normal people to understand. The basic working of the project is depicted in the following figure.
Figure 2.1 – System Diagram
The above diagram clearly explains the scope and use of the Boltay Haath system. The system aims at bridging communication gaps between the deaf community and other people. When fully operational the system will help in minimizing communication gaps, easier collaboration and will also enable sharing of ideas and experiences.
2.1 Performance Measures
The following performance parameters were kept in mind during the design of the project:
‘ Recognition time: A gesture should take approximately 0.25 to 0.second in the recognition process in order to respond in real time.
‘ Continuous and automatic recognition: To be more natural the system must be capable of Recognizing the gestures continuously without any
manual indication or help for demarcating the consecutive gestures.
‘ Recognition Accuracy: The system must recognize the gestures accurately between80 to 90 percent.
2.2 System Architecture
The designed system input hand gestures to the system through an
electronic sensor glove and it identifies the gesture patterns via microcontroller network. Then the identified sign is converted to text and then translated to voice output. The basic components of the All talk Wireless Sign Language Interpreter are given below:
‘ Modules for Gesture Input ‘ Get state of hand (position of fingers, orientation of hand from glove and other sensors and convey to the main software.
‘ Data Transmission Module ‘ Transmit all the data received from all sensors to the gesture processing module.
‘ Gesture Preprocessing Module ‘ Convert raw input into a process-able format for use in pattern matching. In this case, scaled integer values ranging from 0 to 255.
‘ Gesture Recognition Engine ‘ Examines the input gestures for match with a known gesture in the gesture database.
‘ Text To Speech Converter Module ‘ Examines the recognized gestures and converts them into texts as well as to speech.
2.3 Gesture Input
Position and orientation of hand is obtained by two main parts as data glove and sensor arm cover. Data glove consists of 5 potentiometer and one accelerometer as shown in Figure 2.3. Tilt of the palm can be captured by the
accelerometer and the bend of the five fingers can be measured by potentiometer.
Figure 2.2 Accelerometer MMA7260QT
2.4 ISL SIGNS
The sign language into Sub-domains that is English. This is because of the similarity of some gestures. Moreover English contain gestures of words and letters. Gestures have been categorized into Dynamic and Static. In English there are 26 letters. In which two are dynamic and words are of both types one-handed and two-handed. ISL also contains domain specific signs for example computer terms, Environmental terms and Traffic terms. The symbols passed are the equivalent English characters.
Figure 2.3: Equivalent English symbols for Database
CHAPTER-3
Working of P89V51RD2 microcontroller and APR9600
3.1 P89V51RD2 microcontroller
3.1.1 Introduction:
The P89V51RD2 is an 80C51 microcontroller with 64 kB Flash and 1024 bytes of data RAM. Key feature of the P89V51RD2 is its X2 mode option. The design engineer can choose to run the application with the conventional 80C51 clock rate (12 clocks per machine cycle) or select the X2 mode (6 clocks per machine cycle) to achieve twice the throughput at the same clock frequency.
Another way to bene’t from this feature is to keep the same performance by reducing the clock frequency by half, thus dramatically reducing the EMI. The Flash program memory supports both parallel programming and in serial In- System Programming (ISP). Parallel programming mode offers gang- programming at high speed, reducing programming costs and time to market. ISP allows a device to be reprogrammed in the end product under software control.
The capability ‘eld/update the application ‘rmware makes a wide range of
applications possible. The P89V51RD2 is also In-Application Programmable (IAP), allowing the Flash program memory to be recon’gured even while the application is running.
3.1.2 Features:
‘ 80C51 Central Processing Unit
‘ 5 V Operating voltage from 0 to 40 MHz
‘ 64 kB of on-chip Flash program memory with
‘ ISP (In-System Programming) and
‘ Supports 12-clock (default) or 6-clock mode selection via software or
ISP
‘ SPI (Serial Peripheral Interface) and enhanced UART
‘ PCA (Programmable Counter Array) with PWM and Capture/Compare functions
‘ Four 8-bit I/O ports with three high-current Port 1 pins (16 mA each)
‘ Three 16-bit timers/counters
‘ Programmable Watchdog timer (WDT)
‘ Eight interrupt sources with four priority levels
‘ Second DPTR register
‘ Low EMI mode (ALE inhibit)
‘ TTL- and CMOS-compatible logic levels
3.1.3 Block diagram of P89V51RD2 microcontroller
Figure 3.1 : Block diagram of P89V51RD2 microcontroller
3.1.4 Pin Description of P89V51RD2 microcontroller
Port 0:
Figure 3.2 : Pin Description of P89V51RD2 microcontroller
Port 0 is an 8-bit open drain bi-directional I/O port. Port 0 pins that have
‘1’s written to them float, an in this state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external code and data memory. In this application, it uses strong internal pull-ups when transitioning to ‘1’s. Port 0 also receives the code bytes during the external host mode programming, and outputs the code bytes during the external host mode verification. External pull-ups are required during program verification or as a general purpose I/O port.
Port 1:
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 pins are pulled high by the internal pull-ups when ‘1’s are written to them and can be used as inputs in this state. As inputs, Port 1 pins that are externally pulled LOW will source current (IIL) because of the internal pull-ups. P1.5, P1.6, P1.7 have high current drive of 16 mA. Port 1 also receives the low-order address bytes during the external host mode programming and verification.P1.0 1 40 2
I/O.
Port 2:
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins are pulled HIGH by the internal pull-ups when ‘1’s are written to them and can be used as inputs in this state. As inputs, Port 2 pins that are externally pulled LOW will source current (IIL) because of the internal pull-ups. Port 2 sends the high- order address byte during fetches from external program memory and during accesses to external Data Memory that use 16-bit address (MOVX@ DPTR). In this application, it uses strong internal pull-ups when transitioning to ‘1’s. Port 2 also receives some control signals and a partial of high-order address bits during the external host mode programming and verification.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins are pulled HIGH by the internal pull-ups when ‘1’s are written to them and can be used as inputs in this state. As inputs, Port 3 pins that are externally pulled LOW will source current (IIL) because of the internal pull-ups. Port 3 also receives some control signals and a partial of high-order address bits during the external host mode programming and verification.
P3.0 RXD: serial input port
P3.1 TXD: serial output port
P3.2 INT0: external interrupt 0 input
P3.3 INT1: external interrupt 1 input
P3.4 T0: external count input to Timer/Counter 0
P3.5 T1: external count input to Timer/Counter 1
P3.6 WR: external data memory write strobe
P3.7 RD: external data memory read strobe
PSEN (Program Store Enable):-
PSEN is the read strobe for external program memory. When the device is executing from internal program memory, PSEN is inactive (HIGH). When the device is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. A forced HIGH-to-LOW input transition on the PSEN pin while the RST input is continually held HIGH for more than 10 machine cycles will cause the device to enter external host mode programming.
RST (RESET):-
While the oscillator is running, a HIGH logic state on this pin for two machine cycles will reset the device. If the PSEN pin is driven by a HIGH-to- LOW input transition while the RST input pin is held HIGH, the device will enter the external host mode.
EA (EXTERNAL ACCESS ENABLE):-
EA must be connected to VSS in order to enable the device to fetch code from the external program memory. EA must be strapped to VDD for internal program execution. However, Security lock level 4 will disable EA, and program execution is only possible from internal program memory. The EA pin can tolerate a high voltage of 12 V.
ALE/PROG (ADDRESS LATCH ENABLE):-
ALE is the output signal for latching the low byte of the address during an access to external memory. This pin is also the programming pulse input (PROG) for flash programming. Normally the ALE is emitted at a constant rate of 1’6 the crystal frequency and can be used for external timing and clocking. One ALE pulse is skipped during each access to external data memory. However, if AO is set to ‘1’, ALE is disabled.
NC: No Connect
XTAL1 (CRYSTAL 1):- Input to the inverting oscillator amplifier. XTAL2 (CRYSATL 2):- Output from the inverting oscillator amplifier. VDD: Power supply
VSS: Ground
3.1.5 Special function register’ bit addresses
Name Description Bit address
TCON Timer Control Register 88H
T2CON Timer2 Control Register C8H
T2MOD Timer2 Mode Control C9H
TH0 Timer 0 HIGH 8CH
TH1 Timer 1 HIGH 8DH
TH2 Timer 2 HIGH CDH
TL0 Timer 0 LOW 8AH
TL1 Timer 1 LOW 8BH
TL2 Timer 2 LOW CCH
TMOD Timer 0 and 1 Mode 89H
3.1.6 Timers/counters 0 and 1
‘ The two 16-bit Timer/Counter registers: Timer 0 and Timer 1 can be configured to operate either as timers or event counters (see Table 1 and Table 2).
‘ In the ‘Timer’ function, the register is incremented every machine cycle.
Thus, one can think of it as counting machine cycles. Since a machine cycle consists of six oscillator periods, the count rate is 1/6 of the oscillator frequency.
‘ In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled once every machine cycle.
‘ The ‘Timer’ or ‘Counter’ function is selected by control bits C/T in the Special Function Register TMOD. These two Timer/Counters have four operating modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 is different. The four operating modes are described in the following text.
‘ The ‘Timer’ or ‘Counter’ function is selected by control bits C/T in the Special Function Register TMOD. These two Timer/Counters have four operating modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 is different. The four operating modes are described in the following text.
Table 1: TMOD – Timer/Counter mode control register (address 89H) bit allocation
Table 2: TMOD – Timer/Counter mode control register (address 89H) bit description
Table 3: TMOD – Timer/Counter mode control register (address 89H) M1/M0 operating mode
Table 4: TCON – Timer/Counter control register (address 88H) bit allocation
Table 5: TCON – Timer/Counter control register (address 88H) bit description
3.1.7 Main board schematic
Figure 3.3 : Main board schematic
3.2 APR9600
3.2.1 Features
‘ Single-chip, high-quality voice recording & playback solution
– No external ICs required
– Minimum external components
‘ Non-volatile Flash memory technology
– No battery backup required
‘ User-Selectable messaging options
– Random access of multiple fixed-duration messages
– Sequential access of multiple variable-duration messages
‘ User-friendly, easy-to-use operation
– Programming & development systems not required
– Level-activated recording & edge-activated play back switches
‘ Low power consumption
– Operating current: 25 mA typical
– Standby current: 1 uA typical
– Automatic power-down
‘ Chip Enable pin for simple message expansion
3.2.2 General Description
The APR9600 device offers true single-chip voice recording, non-volatile storage, and playback capability for 40 to 60 seconds. The device supports both random and sequential access of multiple messages. Sample rates are user- selectable, allowing designers to customize their design for unique quality and storage time needs. Integrated output amplifier, microphone amplifier, and AGC circuits greatly simplify system design. the device is ideal for use in portable voice recorders, toys, and many other consumer and industrial applications. APLUS integrated achieves these high levels of storage capability by using its proprietary analog/multilevel storage technology implemented in an advanced Flash non-volatile memory process, where each memory cell can store 256 voltage levels. This technology enables the APR9600 device to reproduce voice signals in their natural form. It eliminates the need for encoding and compression, which often introduce distortion.
3.2.3 Pin-out Diagram
Figure 3.4 : APR9600 Pin-out Diagram
3.2.4 Functional Description
The APR9600 block diagram is included in order to give understanding of the APR9600 internal architecture. At the left hand side of the diagram are the analog inputs. A differential microphone amplifier, including integrated AGC, is included on-chip for applications requiring its use. The amplified microphone signal is fed into the device by connecting the Ana_Out pin to the Ana_In pin through an external DC blocking capacitor. Recording can be fed directly into the Ana_In pin through a DC blocking capacitor, however, the connection between Ana_In and Ana_Out is still required for playback. The next block encountered by the input signal is the internal anti-aliasing filter. The filter automatically adjusts its response according to the sampling frequency selected so Shannon’s Sampling Theorem is satisfied. After anti-aliasing filtering is accomplished the signal is ready to be clocked into the memory array. This storage is accomplished through a combination of the Sample and Hold circuit and the Analog Write/Read circuit. These circuits are clocked by either the Internal Oscillator or an external clock source. When playback is desired the previously stored recording is retrieved from memory, low pass filtered, and amplified as shown on the right hand side of the diagram. The signal can be heard by connecting a speaker to the SP+ and SP- pins. Chip-wide management is accomplished through the device control block shown in the upper right hand corner. Message management is controlled through the message control block represented in the lower center of the block diagram. More detail on actual device application can be found in the Sample Applications section. More detail on sampling control can be found in the Sample Rate and Voice Quality section. More detail on message management and device control can be found in the Message Management section.
3.2.5 Block Diagram of APR9600
Figure 3.5 : Block diagram of APR9600
3.2.6 Message Management General Description
Playback and record operations are managed by on chip circuitry. There are several available messaging modes depending upon desired operation. These message modes determine message management style, message length, and external parts count. Therefore, the designer must select the appropriate operating mode before beginning the design. Operating modes do not affect voice quality; for information on factors affecting quality refer to the Sampling Rate & Voice Quality section. The device supports three message management modes (defined by the MSEL1, MSEL2 and /M8_Option pins shown in Figures 1 and 2):
‘ Random access mode with 2, 4, or 8 fixed-duration messages
‘ Tape mode, with multiple variable-duration messages, provides
Two options:
– Auto rewind
– Normal
Modes cannot be mixed. Switching of modes after the device has recorded an initial message is not recommended. If Modes are switched after an initial recording has been made some unpredictable message fragments from the previous mode may remain present, and be audible on playback, in the new mode. These fragments will disappear after a record operation in the newly selected mode. Table 1 defines the decoding necessary to choose the desired mode.
An important feature of the APR9600 message management capabilities is the ability to audibly prompt the user to changes in the device’s status through the use of ‘beeps’ superimposed on the device’s output. This feature is enabled by asserting a logic high level on the BE pin.
Mode MSEL1 MSEL2 M8_Option
Random Access 2 fixed duration messages
0
1
Pull this pin to
VCC through
100K resistor
Random Access 4
fixed duration messages 1 0 Pull this pin to
VCC through
100K resistor
Random Access 8 fixed duration messages 1 1 Becomes the /M8 message trigger input pin
Tape mode,
Normal operation 0 0 0
Tape mode, Auto
rewind operation 0 0 1
3.2.7 Random Access Mode
Random access mode supports 2, 4, or 8 messages segments of fixed duration. As suggested recording or playback can be made randomly in any of the selected messages. The length of each message segment is the total recording length available (as defined by the selected sampling rate) divided by the total number of segments enabled (as decoded in Table1). Random access mode provides easy indexing to message segments.
Functional Description of Recording in Random Access Mode
On power up, the device is ready to record or play back, in any of the enabled message segments. To record, /CE must be set low to enable the device and /RE must be set low to enable recording. You initiate recording by applying a low level on the message trigger pin that represents the message segment you intend to use. The message trigger pins are labeled /M1_Message – /M8_Option on pins
1-9 (excluding Pin7) for message segments 1-8 respectively.
Note: Message trigger pins /M1_Message, /M2_Next, /M7_END, and M8_Option, have expanded names to represent the different functionality that these pins assume in the other modes. In random access mode
these pins should be considered purely message trigger pins with the same functionality as /M3, /M4, /M5,
and /M6. For a more thorough explanation of the functionality of device pins in different modes please refer to the pin description table that appears later in this document.
When actual recording begins the device responds with a single beep (if the
BE pin is high to enable the beep tone) at the speaker outputs to indicate that it has started recording. Recording continues as long as the message pin stays low.
The rising edge of the same message trigger pin during record stops the recording operation (indicated with a single beep).
If the message trigger pin is held low beyond the end of the maximum
allocated duration, recording stops automatically (indicated with two beeps), regardless of the state of the message trigger pin. The chip then enters low-power mode until the message trigger pin returns high. After the message trigger pin returns to high, the chip enters standby mode. Any subsequent high to low transition on the same message trigger pin will initiate recording from the beginning of the same message segment. The entire previous message is then overwritten by the new message, regardless of the duration of the new message. Transitions on any other message trigger pin or the /RE pin during the record operation are ignored until after the device enters standby mode.
Functional Description of Playback in Random Access Mode
On power up, the device is ready to record or playback, in any of the enabled message segments. To playback, /CE must be set low to enable the device and
/RE must be set high to disable recording & enable playback. You initiate playback by applying a high to low edge on the message trigger pin that
representing the message segment you intend to playback. Playback will continue until the end of the message is reached. If a high to low edge occurs on the same message trigger pin during playback, playback of the current message stops
immediately.
3.2.8 Application circuit of APR9600
Figure 3.6 : Application circuit of APR9600
CHAPTER-4
Accelerometer
4.1 ??1.5g – 6g Three Axis Low-g Micro-machined Accelerometer
The MMA7260QT low cost capacitive micro machined accelerometer features signal conditioning, a 1-pole low pass filter, temperature compensation and g-Select which allows for the selection among 4 sensitivities. Zero-g offset full scale span and filter cut-off are factory set and require no external devices. Includes a Sleep Mode that makes it ideal for handheld battery powered electronics.
Figure 4.1 : MMA7260QT Accelerometer
4.2 Features
‘ Selectable Sensitivity (1.5g/2g/4g/6g)
‘ Low Current Consumption: 500?? A
‘ Sleep Mode: 3 ?? A
‘ Low Voltage Operation: 2.2 V ‘ 3.6 V
‘ 6mm x 6mm x 1.45mm QFN
‘ High Sensitivity (800 mV/g @ 1.5g)
‘ Fast Turn on Time
‘ Integral Signal Conditioning with Low Pass Filter
‘ Robust Design, High Shocks Survivability
‘ Environmentally Preferred Package
‘ Low Cost
4.3 Typical Applications
‘ HDD MP3 Player: Freefall Detection
‘ Laptop PC: Freefall Detection, Anti-Theft
‘ Cell Phone: Image Stability, Text Scroll, Motion Dialing, E-Compass
‘ Pedometer: Motion Sensing
‘ PDA: Text Scroll
‘ Navigation and Dead Reckoning: E-Compass Tilt Compensation
‘ Gaming: Tilt and Motion Sensing, Event Recorder
‘ Robotics: Motion Sensing
4.4 Block Diagram
Figure 4.2 : Simplified Accelerometer Functional Block Diagram
Table 5- Maximum Ratings
(Maximum ratings are the limits to which the device can be exposed without causing permanent damage.)
4.5 WARNING: This device is sensitive to electrostatic discharge.
Although the Free-scale accelerometer contains internal 2000 volts ESD protection circuitry, extra precaution must be taken by the user to protect the chip from ESD. A charge of over 2000 volts can accumulate on the human body or associated test equipment. A charge of this magnitude can alter the performance or cause failure of the chip. When handling the accelerometer, proper ESD precautions should be followed to avoid exposing the device to discharges which may be detrimental to its performance.
4.6 Mounting Consideration
Device selection depends on the angle of reference and how the device will be mounted in the end application. This will allow you to achieve the highest degree resolution for a given solution due to the nonlinearity of the technology. First, you need to know what the sensing axis is for the accelerometer.
To obtain the most resolution per degree of change, the IC should be mounted with the sensitive axis parallel to the plane of movement where the most sensitivity is desired. For example, if the degree range that an application will be measuring is only 0?? to 45?? and the PCB will be mounted perpendicular to gravity, then an X-Axis device would be the best solution. If the degree range was
0?? to 45?? and the PCB will be mounted perpendicular to gravity, then a Z-Axis device would be the best solution. This is understood more when thinking about
the output response signal of the device and the nonlinearity.
Figure 4.3 : Sensing Axis for the MMA7260Q Accelerometer with X, Y,And
Z-Axis for Sensing Acceleration
Figure 4.4 : Gravity Component of a Tilted X-Axis Accelerometer
Figure 4.5 : Gravity Component of a Tilted Y- Axis Accelerometer
The typical output of capacitive, micro-machined accelerometers is more like a sine function. The figure shows the analog output voltage from the accelerometer for degrees of tilt from -90?? to +90??. The change in degrees of tilt directly corresponds to a change in the acceleration due to a changing component of gravity acted on the accelerometer. The slope of the curve is actually the sensitivity of the device. As the device is tilted from 0??, the sensitivity decreases. You see this in the graph as the slope of output voltage decreases for an increasing tilt towards 90??. Because of this nonlinearity, the degree resolution of the application must be determined at 0?? and 90?? to ensure the lowest resolution is still within the required application resolution.
4.7 INTERFACING TO ADC
An 8-Bit ADC
An 8-bit ADC cuts 3.3V supply into 255 steps of 12.9mV for each step. Therefore, by taking one ADC reading of the ADC0808 at 0g (0??of tilt for an x- axis device) and 1g (90?? of tilt for an x-axis device), would result in the following:
0??: 1650mV + 12.9mV = 1662.9mV,
Which is 0.92?? resolution.
90??: 2450mV+ 12.9mV = 2462.9mV, Which is 6.51?? resolution.
Due to the nonlinearity discussed earlier, you will see that the accelerometer is most sensitive when the sensing axis is closer to 0??, and less sensitive when closer to 90??. Therefore, the system provides a 0.92 degree resolution at the highest sensitivity point (0 degrees), and a 6.51 degree resolution at the lowest sensitivity point (90??).
4.8 SCHEMATICS ACCELEROMETER
Figure 4.6 : Schematic Accelerometer
CHAPTER-5
ADC0808/ADC0809
5.1 General Description
The ADC0808, ADC0809 data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital converter, 8-channel multiplexer and microprocessor compatible control logic. The 8-bit A/D converter uses successive approximation as the conversion technique. The converter features a high impedance chopper stabilized comparator, a 256R voltage divider with analog switch tree and a successive approximation register. The 8-channel multiplexer can directly access any of 8-single-ended analog signals. The device eliminates the need for external zero and full-scale adjustments. Easy interfacing to microprocessors is provided by the latched and decoded multiplexer address inputs and latched TTL TRI-STATE outputs. The design of the ADC0808, ADC0809 has been optimized by incorporating the most desirable aspects of several A/D conversion techniques. The ADC0808, ADC0809 offers high speed, high accuracy, minimal temperature dependence, excellent long-term accuracy and repeatability, and consumes minimal power. These features make this device ideally suited to applications from process and machine control to consumer and automotive applications. For 16-channel multiplexer with common output (sample/hold port) see ADC0816 data sheet. (See AN-247 for more information.)
5.2 Features
‘ Easy interface to all microprocessors
‘ Operates ratio metrically or with 5 VDC or analog span adjusted voltage reference
‘ No zero or full-scale adjust required
‘ 8-channel multiplexer with address logic
‘ 0V to VCC input range
‘ Outputs meet TTL voltage level specifications
‘ ADC0808 equivalent to MM74C949
‘ ADC0809 equivalent to MM74C949-1
5.3 Key Specifications
‘ Resolution 8 Bits
‘ Total Unadjusted Error ‘? LSB and ??1 LSB
‘ Single Supply 5 VDC
‘ Low Power 15 mW
‘ Conversion Time 100 ??s
5.4 Block Diagram of ADC0808/ADC0809
Figure 5.1 : Block Diagram of ADC0808/ADC0809
The ADC0808, ADC0809 data acquisition component is a monolithic CMOS device with an 8- bit analog-to-digital converter, 8-channel multiplexer and microprocessor compatible control logic. The 8-bit A/D converter uses successive approximation as the conversion technique. The converter features a high impedance chopper stabilized comparator, a 256R voltage divider with analog switch tree and a successive approximation register. The 8-channel multiplexer can directly access any of 8-single-ended analog signals. The device eliminates the need for external zero and full-scale adjustments. Easy interfacing to microprocessors is provided by the latched and decoded multiplexer address inputs and latched TTL TRI-STATE outputs. The design of the ADC0808, ADC0809 has been optimized by incorporating the most desirable aspects of several A/D conversion techniques. The ADC0808, ADC0809 offers high speed, high accuracy, minimal temperature dependence, excellent long-term accuracy and repeatability, and consumes minimal power. These features make this device ideally suited to applications from process and machine control to consumer and automotive applications. For
16-channel multiplexer with common output (sample/hold port) see ADC0816 data sheet.
5.5 Connection Diagrams
Figure 5.2 : Connection diagram of ADC0808CCN or ADC0809CCN
5.6 Functional Description
MULTIPLEXER
The device contains an 8-channel single-ended analog signal multiplexer. A particular input channel is selected by using the address decoder. Table 1 shows the input states for the address lines to select any channel. The address is latched into the decoder on the low-to-high transition of the address latch enable signal.
TABLE 6 : Analog Channel Selection
Page 27
CHAPTER-6
Flex Sensor
The Flex Sensor patented technology is based on resistive carbon elements. As a variable printed resistor, the Flex Sensor achieves great form-factor on a thin flexible substrate. When the substrate is bent, the sensor produces a resistance output correlated to the bendradius’the smaller the radius, the higher the resistance value.
6.1 What are the Flex Sensors ?
Flex sensors are sensors that change in resistance depending on the amount of bend on the sensor. They convert the change in bend to electrical resistance the more the bend, the more the resistance value. They are usually in
the form of a thin strip from 1”-5” long that vary in resistance.They can be made uni-directional or bi-directional.
Sizes: 1. 1k’ to 20k’
2. 50k’ to 50
3. 50k’ to 200k’
6.2 How Flex Sensors work ?
‘ Flex sensors are analog resistors
‘ They work as variable analog voltage dividers
‘ Inside the flex sensors are carbon resistive elements within a thin flexible substrate
‘ When the substrate is bent the sensor produces a resistance output relative to the bend radius.
Figure 6.1 : Flex sensors
6.3 Application
‘ Robotics : Flex sensors may be used to determine joint movement or placement.
‘ Bio-metrics : The sensor can be placed on a moving joint of athletic equipment to provide an electrical indication of movement or
placement.
‘ Flex sensors are also used for auto controls, Fitness products, measuring devices, assistive technology, musical instruments, joysticks etc.
CHAPTER- 7
16×2 LCD
7.1 LCD Display with 2 lines x 16 characters
It is connected to microcontroller through 16 wires
‘ RS/RD-WT/EN PINS ARE CONTROL PINS
‘ D4-D5-D6-D7 DATA PINS
‘ R-W CONNECTED TO GROUND FOR SENDING DATA FROM MINCROCONTROLLER TO LCD.
‘ RS=0 FOR INSTRUCTION EXECUTION
‘ RS=1 FOR DATA DISPLAY
‘ EN PULSE TRANSFERS DATA TO LCD RAM
‘ PIN 15-16 BACKLITE INPUT FOR READING IN NIGHT CONDITIONS
7.2 LCD Pins Description:
LCD used has 14 pins. Functions of each pin are given in below tables.
-Vcc, Vss and Vee. While Vcc and Vss provides +5volts and ground respectively. Vee is used for controlling LCD contrast.
-RS, Register Select
There are two very important registers inside the LCD. RS pin is used for their selection as follow. If RS=0 the instruction command code register is selected allowing user to send a command such as a clear display cursor at home etc. If
RS=1 the data register is selected is allowing use to send data to be displaying on the LCD.
-R/W, Read Write
R/W input allows the user to write information to the LCD or read information
from it. R/W=1 when reading. R/W=0 when writing.
-E, Enable
LCD to latch information presented to its data pins uses the enable pin. When data is supplied to data pins a high to low pulse must be supplied to these pins in
order for the LCD to latch in data present at the data pins. This pulse must be of
450 ns wide.
-D0-D7
The 8bit data pins are used to send information to LCD or read the content of
LCD internal registers to display letters and numbers we send ASCII code for the numbers A-Z, a-z and 0-9 to these pins while making RS=1.
There also instructions commands codes that can be send to LCD to clear display
or force the cursor to home position or blinking the cursor.
HOW INSTRUCTION IS EXECUTED?
– RS=0 for instruction
– Put data on data line
– EN pulse applied, instruction will be executed
7.3 Need for LCD display:
LED or other this due to the following reasons.
1. The declining prizing of LCDs.
2. The ability to display numbers characters and graphics. This is in contrast to LEDs, In recent years the LCD is finding wide spread use replacing LEDs seven segment which are limited to numbers and few characters.
3. Incorporation of a refreshing controller into LCD thereby relieving the CPU of task of refreshing of LCD. In contrast CPU to keep displaying data must refresh LED.
4. Ease of programming characters and graphics.
7.4 Features of LCD display:
– Easy interface with 4 it or 8-bit MPU.
– Built in dot matrix LCD controller with 5×7 or 5×10 character font.
– Built in character generated ROM, when provides 160 characters with 5×7 dots and 32 characters with fonts 5×10 dots.
– Internal CG RAM for user defined fonts 5×7 or 5×10
– Internal automatic reset circuit at power on.
– Built in oscillator circuit
– Wide Ranges of instructions functions are: Clear Display, Cursor
Home, Display on/off, Cursor shift, and Display shift.
7.5 LCD Command codes:
7.6 Functional Diagram
Figure 7.1 : Functional Diagram
CHAPTER-8
Software Implementation
;P0 IS FOR LCD 8 BIT DATAOUTPUT
;P2.5,P2.6,P2.7 LCD CONTROL SIGNAL AS MAZIDI BOOK
;P1 FOR ADC DATA
;P2.3 FOR CHANNEL SEL
;p2.4 for channel sel
;P2.0 FOR ALE AND SC
; 0E DIRECT 5 VDC
;CH0 FLEX 1
;CH1 FLEX 2
;CH2 FLEX 3
;CH3 X
;CH4 Y
;CH5 Z
.ORG 0000H LJMP MAIN
.ORG 0050H MAIN: MOV SP,#69H
MOV P1,#0FFH ;MAKE P1 AS ADC INPUT SETB P3.2
SETB P3.3
SETB P3.4
SETB P3.5
SETB P3.7
SETB P3.0
SETB P3.1
CLR P2.1
MOV 41H,#01
MOV 42H,#250
MOV 43H,#45
MOV 44H,#35
MOV P1,#0FFH
CLR P2.0
CLR P2.3
CLR P2.4
CLR 00H CLR 01H
MOV 31H,#00H MOV 32H,#00H MOV 33H,#00H MOV 34H,#00H MOV 35H,#00H
MOV 51H,#00H MOV 52H,#00H MOV 53H,#00H MOV 54H,#00H MOV 55H,#00H MOV 56H,#00H MOV 57H,#00H MOV 58H,#00H
MOV 60H,#00H MOV 61H,#00H MOV 62H,#00H MOV 63H,#00H MOV 64H,#00H MOV 65H,#00H MOV 66H,#00H MOV 67H,#00H MOV 68H,#00H
ACALL M_DISP LCALL DELAY_2
ACALL LCD_SETUP
AGAIN: CLR P2.3
CLR P2.4
CLR P2.2
LCALL DELAY SETB P2.0
LCALL DELAY CLR P2.0
LCALL DELAY
MOV A,P1
MOV 31H,A LCALL DELAY
SETB P2.3
CLR P2.4
CLR P2.2
LCALL DELAY SETB P2.0
LCALL DELAY CLR P2.0
LCALL DELAY
MOV A,P1
MOV 32H,A
LCALL DELAY SETB P2.4
CLR P2.3
CLR P2.2
LCALL DELAY SETB P2.0
LCALL DELAY CLR P2.0
LCALL DELAY
MOV A,P1
MOV 33H,A
LCALL DELAY SETB P2.2
CLR P2.4
CLR P2.3
LCALL DELAY SETB P2.0
LCALL DELAY
CLR P2.0
LCALL DELAY MOV A,P1
MOV 35H,A
ACALL RLY_CHK_1
ACALL RLY_CHK_2
ACALL RLY_CHK_3
ACALL RLY_CHK_4
MOV A,31H ACALL CONV1
ACALL DISPLAY_R
MOV A,32H ACALL CONV1
ACALL DISPLAY_Y
MOV A,33H ACALL CONV1
ACALL DISPLAY_B MOV A,35H ACALL CONV1
ACALL DISPLAY_D LCALL DELAY MOV A,54H
CJNE A,#01H,GHR1
MOV A,51H CJNE A,#00H,GHR1
MOV A,52H
CJNE A,#01H,GHR1
MOV A,53H CJNE A,#01H,GHR1
ACALL SIGNA LJMP GHREE
GHR1: MOV A,54H
CJNE A,#01H,GHR2
MOV A,51H CJNE A,#01H,GHR2
MOV A,52H CJNE A,#01H,GHR2
MOV A,53H CJNE A,#01H,GHR2
ACALL SIGNC LJMP GHREE
GHR2: MOV A,54H
CJNE A,#00H,GHR3
MOV A,51H CJNE A,#00H,GHR3
MOV A,52H CJNE A,#00H,GHR3
MOV A,53H
CJNE A,#01H,GHR3
ACALL SIGNG LJMP GHREE
GHR3: MOV A,54H
CJNE A,#00H,GHR3A MOV A,51H
CJNE A,#00H,GHR3A
MOV A,53H CJNE A,#00H,GHR3A MOV A,55H
CJNE A,#00H,GHR3A ACALL SIGNH LJMP GHREE
GHR3A: MOV A,54H CJNE A,#01H,GHR3B
MOV A,51H CJNE A,#01H,GHR3B MOV A,52H
CJNE A,#00H,GHR3B
MOV A,53H CJNE A,#01H,GHR3B ACALL SIGN1
LJMP GHREE GHR3B: MOV A,54H
CJNE A,#01H,GHR3AB
MOV A,51H
CJNE A,#01H,GHR3AB MOV A,52H
CJNE A,#00H,GHR3AB MOV A,53H
CJNE A,#00H,GHR3AB
ACALL SIGN2
LJMP GHREE GHR3AB: MOV A,54H
CJNE A,#01H,GHR3AB1
MOV A,51H
CJNE A,#00H,GHR3AB1
MOV A,52H
CJNE A,#00H,GHR3AB1
MOV A,53H
CJNE A,#00H,GHR3AB1
ACALL SIGN3
LJMP GHREE GHR3AB1:
GHREE:
LJMP AGAIN CONV1: MOV R2,#00H
MOV R3,#00H
MOV R4,#00H
MOV B,#10 ;divide by 10
DIV AB
MOV R2,B ;save low digit MOV B,#10 ;divide by 10 once more DIV AB
ORL A,#30H ;make it ASCII MOV R4,A ;save MSD MOV A,B
ORL A,#30H ;make 2nd digit an ASCII MOV R3,A ;save it
MOV A,R2
ORL A,#30H ;make 3rd digit an ASCII MOV R2,A ;save the ASCII
RET
DISPLAY_R:MOV A,#0C0H ;LINE 1 POSITION 10
ACALL COMMAND ;issue command
MOV A,R4
ACALL DATA_DISPLAY MOV A,R3
ACALL DATA_DISPLAY MOV A,R2
ACALL DATA_DISPLAY
RET
DISPLAY_Y:MOV A,#0C4H ;LINE 1 POSITION 10
ACALL COMMAND ;issue command
MOV A,R4
ACALL DATA_DISPLAY MOV A,R3
ACALL DATA_DISPLAY MOV A,R2
ACALL DATA_DISPLAY
RET
DISPLAY_B:MOV A,#0C8H ;LINE 1 POSITION 10
ACALL COMMAND ;issue command
MOV A,R4
ACALL DATA_DISPLAY MOV A,R3
ACALL DATA_DISPLAY MOV A,R2
ACALL DATA_DISPLAY
RET
DISPLAY_D:MOV A,#0CCH ;LINE 1 POSITION 10
ACALL COMMAND ;issue command
MOV A,R4
ACALL DATA_DISPLAY MOV A,R3
ACALL DATA_DISPLAY MOV A,R2
ACALL DATA_DISPLAY
RET
SIGNA: MOV A,#89H ;LINE 1 POSITION 10
ACALL COMMAND ;issue command
MOV A,#’"’ ACALL DATA_DISPLAY
MOV A,#’A’ ACALL DATA_DISPLAY MOV A,#’"’
ACALL DATA_DISPLAY RET
SIGNC: MOV A,#89H ;LINE 1 POSITION 10
ACALL COMMAND ;issue command
MOV A,#’"’ ACALL DATA_DISPLAY
MOV A,#’C’ ACALL DATA_DISPLAY MOV A,#’"’
ACALL DATA_DISPLAY RET
SIGNG: MOV A,#89H ;LINE 1 POSITION 10
ACALL COMMAND ;issue command
MOV A,#’"’ ACALL DATA_DISPLAY MOV A,#’G’
ACALL DATA_DISPLAY MOV A,#’"’
ACALL DATA_DISPLAY RET
SIGNH: MOV A,#89H ;LINE 1 POSITION 10
ACALL COMMAND ;issue command
MOV A,#’"’ ACALL DATA_DISPLAY
MOV A,#’H’ ACALL DATA_DISPLAY
MOV A,#’"’ ACALL DATA_DISPLAY RET
SIGN1: MOV A,#89H ;LINE 1 POSITION 10
ACALL COMMAND ;issue command
MOV A,#’"’ ACALL DATA_DISPLAY MOV A,#’1′
ACALL DATA_DISPLAY MOV A,#’"’
ACALL DATA_DISPLAY
RET
SIGN2: MOV A,#89H ;LINE 1 POSITION 10
ACALL COMMAND ;issue command
MOV A,#’"’ ACALL DATA_DISPLAY
MOV A,#’2′ ACALL DATA_DISPLAY MOV A,#’"’
ACALL DATA_DISPLAY RET
SIGN3: MOV A,#89H ;LINE 1 POSITION 10
ACALL COMMAND ;issue command
MOV A,#’"’ ACALL DATA_DISPLAY
MOV A,#’3′ ACALL DATA_DISPLAY
MOV A,#’"’
ACALL DATA_DISPLAY RET
RLY_CHK_1: MOV A,31H CJNE A,#190D,NO_25
MOV 51H,#00H RET
NO_25: JNC MOR_25
MOV 51H,#00H RET
MOR_25: MOV 51H,#01H RET
RLY_CHK_2: MOV A,32H CJNE A,#196D,NO_25A
MOV 52H,#00H RET
NO_25A: JNC MOR_25A
MOV 52H,#00H RET
MOR_25A: MOV 52H,#01H
RET RLY_CHK_3: MOV A,33H
CJNE A,#190D,NO_25_AA MOV 53H,#00H
RET
NO_25_AA: JNC MOR_25_AA MOV 53H,#00H
RET
MOR_25_AA:
MOV 53H,#01H RET
RLY_CHK_4: MOV A,35H CJNE A,#92D,NO_25X
MOV 54H,#00H
RET
NO_25X: JNC MOR_25X MOV 54H,#00H
RET MOR_25X: MOV 54H,#01H
RET
LCD_SETUP: MOV A,#38H ;init. LCD 2 lines,5×7 matrix
ACALL COMMAND ;issue command MOV A,#0CH ;LCD on, cursor off ACALL COMMAND ;issue command MOV A,#01H ;clear LCD command ACALL COMMAND ;issue command MOV A,#06H ;shift cursor right ACALL COMMAND ;issue command
MOV R0,#80H ;cursor: line 1, pos. 0
MOV DPTR,#L1 ;data from l1 to dptR ACALL FLASH
MOV R0,#0C0H ;cursor: line 1, pos. 0
MOV DPTR,#L1A ;data from l1 to dptR ACALL FLASH
RET
M_DISP: MOV A,#38H ;init. LCD 2 lines,5×7 matrix ACALL COMMAND ;issue command MOV A,#0CH ;LCD on, cursor off ACALL COMMAND ;issue command MOV A,#01H ;clear LCD command ACALL COMMAND ;issue command
MOV A,#06H ;shift cursor right
ACALL COMMAND ;issue command
MOV R0,#80H ;cursor: line 1, pos. 0
MOV DPTR,#L1B ;data from l1 to dptR ACALL FLASH
MOV R0,#0C0H ;cursor: line 1, pos. 0
MOV DPTR,#L1C ;data from l1 to dptR ACALL FLASH
RET
FLASH: MOV A,R0 ;PUT LINE ADDRESS FROM R0 IN TO ACC ACALL COMMAND ;command subroutine
LOOP: CLR A
MOVC A,@A+DPTR JZ OUT
ACALL DATA_DISPLAY
INC DPTR SJMP LOOP
OUT: RET
;P2.1 = WR (start conversion needs to L-to-H pulse)
;P2.7 When low, end-of-conversion)
;P2.0 = RD (a H-to-L will read the data from ADC chip)
;P1.0 – P1.7 = D0 – D7 of the ADC804
COMMAND: ACALL READY ;is LCD ready?
MOV P0,A ;issue command code
CLR P2.5 ;RS=0 for command CLR P2.6 ;R/W=0 to write to LCD SETB P2.7 ;E=1 for H-to-L pulse CLR P2.7 ;E=0 ,latch in
RET
DATA_DISPLAY:
ACALL READY ;is LCD ready?
MOV P0,A ;issue data
SETB P2.5 ;RS=1 for data
CLR P2.6 ;R/W=0 to write to LCD SETB P2.7 ;E=1 for H-to-L pulse
CLR P2.7 ;E=0, latch in
RET
READY:
SETB P0.7 ;make P1.7 input port
CLR P2.5 ;RS=0 access command reg
SETB P2.6 ;R/W=1 read command reg
;read command reg and check busy flag
BACK1: CLR P2.7 ;E=1 for H-to-L pulse
SETB P2.7 ;E=0 H-to-L pulse
JB P0.7,BACK1 ;stay until busy flag=0
RET
DELAY: MOV 10H,#01H C1: MOV 11H,#80H B1: MOV 12H,#255
A1: DJNZ 12H,A1
DJNZ 11H,B1
DJNZ 10H,C1
RET DELAY_1: MOV 13H,#01H
C11: MOV 14H,#9FH
B11: MOV 15H,#0FFH A11: DJNZ 15H,A11
DJNZ 14H,B11
DJNZ 13H,C11
RET
DELAY_2: MOV 23H,#07H C111: MOV 21H,#0FFH B111: MOV 22H,#0FFH A111: DJNZ 22H,A111
DJNZ 21H,B111
DJNZ 23H,C111
RET
L1B: .DB " WELCOME TO ",0
L1C: .DB " SMFD & D ",0
L1: .DB " SIGN:- ",0
L1A: .DB " ",0
.END
CHAPTER-9
Future Enhancements
1. Designing of wireless transceiver system for ‘Microcontroller and Sensors
Based Gesture vocalizer’.
2. Designing of a whole jacket, which would be capable of vocalizing the gestures and movements of animals.
3. Virtual reality application e.g., replacing the conventional input devices like joy sticks in videogames with the data glove.
4. The Robot control system to regulate machine activity at remote sensitive sites.
6.1 Conclusion
Chapter:6
Summary Analysis
It is describes the design and working of a system which is useful for dumb, deaf and blind people to communicate with one another and with the normal people. The dumb people use their standard sign language which is not easily understandable by common people and blind people cannot see their gestures. This system converts the sign language into voice which is easily understandable by blind and normal people. The sign language is translated into some text form, to facilitate the deaf people as well. This text is display on LCD.
6.2 References
1. www.bibsonomy.org
2. www.ieeexplore.ieee.org
3. www.citeulike.org
4. www.researchgate.net
5. R.S Pressman, Software Engineering: A Practitioner’s Approach, Fourth
Edition, McGraw-HILL International, 1997.
6. Srinivas Gutta, Jeffrey Huang, Ibrahim F. Imam, and Harry Wechsler, ‘Face
And Hand Gesture Recognition Using Hybrid Classifiers’.
7. Seong-Whan Lee, ‘Automatic Gesture Recognition for Intelligent Human- Robot Interaction’ Proceedings of the 7th International Conference on Automatic Face and Gesture Recognition.
8. 8051- Micro-controller and embedded system using assembly and C
‘MUHAMMAD ALI MAZIDI’. Second Edition ‘ 2000.