1. INTRODUCTION
1.1 General Introduction
Power electronic converters especially PWM driven inverters are gaining popularity day by day as they have various applications in both domestic and industrial purposes due to their salient features like lesser power consumption, better efficiency, and high quality voltage output along with less maintenance cost.
Renewable energy becomes a challenging aspect for now and future of word due to its increasing demands. Since last three decades, there is a growing effort t make renewable energy more feasible due to its particular characteristics and high cost.
Among renewable energy sources photovoltaic energy is one of the most considerable sources because of its advantages like being widely available and cost free, clean and abundant. Furthermore, being a semiconductor device it’s free of moving parts which results in little operation and maintenance cost. PV cell is especially attractive for application in where sunshine is available for most of the time. Such a system generates electricity by converting the sun’s energy directly into electricity.
The electricity generated by the photo voltaic cell is purely DC in nature. So for its proper applications and usage it needs to be converted into alternating type. As a result of which the concept of inverter came into the picture. Earlier the conventional two level inverters are used which are capable of converting the fixed dc voltage to two level output i.e. +V and –V. But this model proved to be inefficient in terms of delivering maximum power to the output due to its high losses.
For high power and medium voltage applications, it’s quite irrelevant and uneconomical to use conventional inverter as it would cause deterioration of the system longevity and performance. So in order to overcome above problems the concept of multilevel inverter comes in to picture. A multilevel inverter can not only be used to introduced in high power medium voltage application like driving a motor, mills or for traction purposes but also it’s the most cost effective option to meet lower power applications with the help of renewable energy sources such as photo-voltaic cell, wind and fuel cells etc.
1.2 Literature Survey
For industrial purposes a power conversion device with high voltage rating is required. So for this reason, high voltage rating two level inverters were designed with switches like gate turn off thyristor (GTO), integrated gate commutated thyristor (IGCT) and integrated gate bipolar transistor (IGBT) and are connected in series to withstand high voltage. Later it’s came to the notice that the voltage across the series connected switches are uneven, in some switches the voltage across it is even higher than the blocking voltage of the switch which causes unhealthy operation of the system.
In industrial applications also these inverters fails to impress due to its inability to drive the heavy loads because the system large amount of power [1] which suggests that either the voltage or the current need to be large enough. But this increase in power due to rise in current leads to increase in switching current, which is undesirable. Although the rise in voltage is somehow favorable in terms of improvement in performance of installation, but at times it becomes difficult to handle the switching devices due to high voltage stress across them as a result of which they undergo deterioration of their performance [2-5].
To get high quality output voltage the output waveform of the inverter should contain very less ripple component and should be more and more close to sinusoidal waveform. This strategy requires high switching frequency with various pulse width modulation techniques (PWM).
During the mid 70’s a pattern describing an inverter topology capable of producing stepped alternating waveform from various dc voltage source, was published by Baker and Bannister. Later in 90’s various classification of multilevel inverter have been made with different topologies. Till date hundreds of research papers have been published to describe the three main topology of a multilevel inverter (MLI) i.e. (i) Neutral point clamped MLI, (ii) Flying capacitor type MLI and (iii) Cascaded H-Bridge MLI.
The first designed model was series H-bridge [7]. The main drawback of this model is that the voltage stress across the switches of the series connected H-bridges are not similar, in some cases it’s even higher than the reverse blocking voltage of the switch. The above shortcoming leads to the invention of Neutral point clamped MLI (NPCMLI). Basically the NPCMLI that was proposed at the beginning by Baker and Bannister was five level type which was nothing but the slight modification of conventional two level inverter with addition of two more power switches in order to reduce the voltage stress across the switches by providing same DC linked voltages with the help of capacitors. The main idea behind this topology was to make the output waveform more stepped and more sinusoidal by increasing the numbers of switches. But this is not the case the NPCMLI requires proportional numbers of clamping diodes with the increase n numbers of switches which makes the circuit complex, increases the loss due to power switches and requires high protection which intern increases the overall cost of the product. Apart from that this circuit suffers with voltage imbalance problem in their DC linked capacitors. Therefore, for optimal and most economical purpose the use NPCMLI is limited up to three levels only [8].
Inability of neutral point clamped model make the way for the introduction of a new model termed as Flying Capacitor MLI (FCMLI). The main reason behind the preference of FCMLI over NPCMLI is it can generate much higher voltage levels easily and economically. But this model has also certain drawbacks like requirement of large capacitor bank, pre-charging of capacitors and voltage imbalance between individual capacitors which make this model inefficient and uneconomical for higher voltage level output.
After the failure of FCMLI a new model termed as Cascaded H-Bridge model (CHB) catch a great deal of interest among the users as this model circuitry is less complex, output waveform is more and more symmetrical with very less distortion and above all voltage balancing is not a major issue here. This CHBMLI also allows soft switching and simple voltage balancing modulation by which mean the switching strategy can be change or modified in order to reduce the loss across the switches. The CHB model is of two types i.e. symmetrical Cascaded H-bridge model and asymmetrical H-Bridge model. Symmetrical type CHB uses identical and isolated DC voltage sources and it has advantage of having high degree of modularity. However at times it’s very difficult to get identical voltage sources and higher numbers of power electronic switches for higher voltage levels which makes the circuit complex and very cost ineffective mean for use. On the other hand asymmetrical CHB offers a high numbers of output voltage levels with same numbers of but different voltage sources. Because of which this topology looses modularity and employment of different voltage sources raises voltage stress across the switches [9]. Cascaded H-Bridge model is comes out to be the best among all these topologies still it’s circuit gets complicated and draws more power form the supply due to switching losses in case of higher level inverter.
In order to get over the above problem the cascaded H-Bridge inverter is modified to introduce cascaded H-Bridge inverter with reduced numbers of switches (CHBRSMLI). This inverter has characteristic similar to that of CHBMLI with comparatively less distortion, ripple and comparatively less switching loss. Apart from that this model also employs the soft switching and simple voltage balancing modulation techniques.
Now a day’s researches are being carried out to enhance the output of multilevel inverter either by modifying the model or by modifying the switching algorithm. But the modification of the switching algorithm will increase the overall cost of the inverter, and sometimes the modified switching algorithm becomes unsuitable for other converter types. Considering this limitations the in this paper the comparative analysis of various topologies of three different level inverters is presented by keeping total harmonic distortion (THD), distortion factor, required component and circuit complexity as the basic factors for analysis. By providing proper switching sequence the correct angles are obtained and the voltage THD is kept at minimal value as a result of which the quality of output voltage reach higher level. The switching sequences given in this paper can be extensible for some other inverters. These switching sequences are applied on different inverter and verified in MATLAB/SIMULINK environment and their reports are presented.
1.3 MOTIVATION OF WORK
The main intension behind the writing of this paper is based upon 3 things. Firstly, a complete study of various topologies of three different level inverters, second the comparative analysis of these topologies based on different factors like THD, distortion factor and circuit complexity on MATLAB/SIMULINK environment and finally the evaluation of best suitable inverter for real life applications.
1.4 ORGANISATION OF THE REPORT
2. 1 Multilevel inverters topologies
It’s a power electronic device that converter that converts dc power in to AC power of desired voltage and frequency. Multilevel inverters gain high popularity in the field of industrial application as well as in domestic application these days. These inverters generate stepped alternating voltages close to sinusoidal type, from several fixed dc input sources. These input sources generally include renewable sources like PV cell, fuel cells, capacitor voltage sources etc. There are three major types of MLI for industrial applications, i.e. Neutral Point Clamped MLI (NPCMLI), Flying Capacitor MLI (FCMLI) and Cascaded H-bridge MLI (CHBMLI). The multilevel inverters are central area of discussion of this chapter and however, they are sometimes used for rectifying purposes also. The inverters that are mentioned above are used for particular purposes due to their variation in structures and their drawbacks. Structures and characteristics of different inverter topologies are discussed below.
The dc bus capacitors constitute energy pool for the inverter providing energy to some nodes of the inverter to which it’ connected. Each capacitor in the DC bus capacitors have same voltage rating given by Vc = Vdc/(n-1) ; where n is the voltage level.
2.2 NEUTRAL POINT CLAMPED MLI (NPCMLI)
Neutral point clamped or diode clamped inverter is the most commonly used topology. This model employs clamping diodes to clamp the dc voltage in order to generate stepped AC voltage. The main function of the clamping diode is to reduce the voltage stress across the capacitors. The concept of diode clamped inverter was first proposed by Nabae and his co workers in 1981. They showed the working of a three level diode clamped inverter. Basically a three level diode clamped inverter consists of two pairs of switches and two clamping diodes. Here both the clamping diodes provide access to the midpoint voltage. In a three phase NPCMLI all the phase has a common dc linked voltage source which consists of n-1 numbers of dc bus capacitors for a n level inverter. In case of three-level inverter the two dc bus capacitors C1 and C2 are responsible for splitting the dc voltage in to equal two halves. The voltage stress across each switch is limited to Vdc due to the presence of clamping diodes D1 and D2 as shown in figure 2.1. For a three level inverter if Vdc is supposed to be the dc voltage than the midpoint of the dc bus capacitors or each capacitor would have a voltage of Vdc/2 i.e. Vc1=Vc2=Vdc/2. A three level inverter has three different voltage output levels i.e. +Vdc/2, 0 and – Vdc/2. To generate this voltage levels always a pair different switches operates in case of three-level inverter and four switches operates at a time in case of five-level. The switching pattern of three-level NPC inverter is given in the table below.
Table 2.1 switching sequence of three-level inverter
An ‘n’ level diode clamped inverter will require 2(n-1) numbers of power switches, (n-1)*(n-2) numbers of clamping diode and (n-1) numbers of dc linked capacitors to generate the stepped voltage waveform. As the required voltage level increase the number of this clamping diodes, dc bus capacitors and switches increases and makes the circuit more complex. Higher level NPC associated with voltage balancing problem. Apart from that for higher level NPC the reverse recovery voltage becomes a major issue if the inverter is driven by PWM technique.
2.2.1OPERATION OF NPCMLI
A three level NPCMLI is show in the figure 2.1.a, has two pairs of power switches, i.e. S1,S2,S1’and S2’, two clamping diodes D1 and D2 that provide direct access to the midpoint and two dc bus capacitors C1 and C2 that splits the dc bus voltage into two halves and three levels. The voltage levels are +Vdc/2, 0, -Vdc/2. The output voltage +Vdc/2 is obtained when the S1 and S2 are turned on, the output voltage Vo= -Vdc/2 when the switches S1’ and S2’ are turned on and the Vo=0 whenever S2 and S1’ are on [RODRIGUEZ 2002].
The centre of attraction of the NPCMLI is the clamping diodes which clamp the voltage to half of the dc input voltage. Whenever the switches S1 and S2 are on the voltage across the other pair of switch is Vdc which is balanced by the diode D1’. In this case S1’ blocking the voltage across C1 and S2’ blocking the voltage across C2. Here it can be noticed that voltage across output port is ac where as voltage across the switches is dc which is more than output voltage by Vdc/2. If the output is supposed to be taken between the two switches than it would be a dc/dc converter with Vdc, Vdc/2 and 0 as its three voltage levels. Similarly the switching operations for the five level Npc can be drawn as
• For voltage Vo= Vdc/2, all upper switches on i.e. S1-S4
• For voltage Vo= Vdc/4, three upper switches S2-S4 and one lower switch S1’ is on
• For voltage Vo= 0, two upper switches from. S3-S4 and two lower switches from S1’-S2’ are on
• For voltage Vo=- Vdc/4, one upper switch S4 and three lower switches S1’-s3’ are on
• For voltage Vo= -Vdc/2, all lower switches on i.e. S1’-S4’
Table 2.2 five-level NPC switching states.
2.2.2 FEATURES
• High voltage rating required for blocking diodes
Each active switching device has a blocking capacity of Vdc/(n-1) and the clamping diodes need to have different voltage ratings for reverse blocking mode because the reverse blocking voltage across all diodes are not same. Sometimes the certain diodes block a higher fraction of input dc voltage whereas other blocks much lower fraction.
• Dissimilar device rating
All the switches of a NPCMLI don’t conduction for same period. Certain switches conduct for almost entire time period. As a result of which some switches that operate for maximum time would get over sized and other that operate for minimal time would get undersized if the inverter is designed by keeping average duty cycle for all switches. This feature is advantageous because it protects the circuit from damages.
• Capacitor voltage unbalancing
The charging time of each capacitor is not same. Such capacitors cause voltage unbalancing problem. This voltage unbalancing problem can be solved in various ways like replacing that capacitor with a controlled constant dc voltage sources, but this methods sometimes become uneconomical. So for high power uses the switching frequency must be kept minimal to reduce the switching losses and electromagnetic interference problems. However operating at zero power factor the capacitors have equal charging and discharging time in an complete cycle, which results in maximum transfer of reactive power without voltage unbalancing problem.
2.2.3 ADVANTAGES AND DISADVANTAGES
• Advantages
There is always common dc bus capacitors for different phases of that particular inverter
Capacitors can be pre-charged as a group.
The efficiency of the inverter high for fundamental switching frequency.
There is no need of filters for higher voltage level as ripple components are significantly reduced.
• Disadvantages
Real power transfer is difficult due to voltage unbalancing problem of capacitors.
The clamping diodes numbers increases in a quadratic manner as voltage level increases, which makes the circuit impractical for use.
2.3 FLYING CAPACITOR MLI
From the research it’s found that the application of NPCMLI is limited up to three levels only for all major applications. So to overcome the above problem in during 1990 Meynard and Foch bring the concept of flying capacitor model. Flying capacitor model is more developed form of MLI. It uses balancing capacitors instead of clamping diodes as a result of which the power loss due to the switches reduced greatly. A FCMLI consists of (n-1)*(n-2)/2 numbers of capacitors connected in a ladder fashion, where the voltage of each capacitors differs from others for an n level MLI. The voltage gradient between two consecutive capacitors gives the information regarding the step size of output voltage.
2.3.1 Operation of FCMLI
In the figure 2.2.a a flying three-level flying capacitor model is shown which consists of four power switches S1,S2,S1’ and S2’, two dc bus capacitors and a balancing capacitor. The role of the independent balancing capacitor is same as of diode in NPCMLI, to clamp the input voltage to half of its original. The inverter in figure 2.2.a provide three level output i.e. Vdc/2, 0, -Vdc/2. For output voltage Vdc/2 switches S1 and S2 need to be turned on, for –Vdc/2 switches S1’ and S2’ need to be switched on and for 0 output voltage any of the switching pair between S1,S1’ or S2,S2’ need to be turned on. The clamping capacitor C1 is charged when the switches S1 and S1’ is turned on and is discharged when S2 and S2’ pair is operating. The charge of C1 can be balanced by proper selection of 0-level switch combination. This topology provides more flexible switching sequence for higher voltage levels. As it can be seen from the five level phase leg a output with respect to n can be synthesized from various switching sequence.
For voltage level Van=Vdc/2 turn on all upper switches S1-S4
For voltage level Van = Vdc/4 three combinations possible
S1, S2, S3,S1’(Van= Vdc/2 from upper C4’s and -Vdc/4 of C1)
S2, S3, S4,S4’(Van= 3Vdc/4 from upper C3’s and -Vdc/2 of C4)
S1, S2, S3,S1’(Van= Vdc/2 from upper C4’s and -3Vdc/4 of C3’s and Vdc/4 og C2’s)
For voltage level Van=0 there are six combinations
S1, S2. S1’, S2’ (Van=Vdc/2 from C4’s and –Vdc/2 from C2’s)
S3, S4. S3’, S4’ (Van=Vdc/2 from C2’s and –Vdc/2 from C4’s)
S1, S3. S1’, S3’ (Van=Vdc/2 from upperC4’s, –3Vdc/4 from C3’s, +Vdc/2 from C2 and –Vdc/4 from C1)
S1, S4. S2’, S3’ (Van=Vdc/2 from C4’s and –3Vdc/4 from C3’s and Vdc/4 from C1)
S2, S4. S2’, S4’ (Van=3Vdc/4 from C3’s and –Vdc/2 from C2’s +Vdc/2 from c1 and –Vdc/4 from C4)
S3, S1. S3’, S4’ (Van=3Vdc/4 from C3’s and –Vdc/2 from C2’s and –Vdc/2 from C4)
For voltage level Van = -Vdc/4 three combinations possible
S1, S1’, S2,S3’(Van= Vdc/2 from C4’s and -3Vdc/4 of C3)
S4, S2’, S3,S4’(Van= Vdc/4 from C1’s and Vdc/2 of C4)
S3, S1’, S3,S4’(Van= Vdc/2 from C2’s and -Vdc/4 of C1 and –Vdc/2 from C4)
For voltage level Van=-Vdc/2 turn on all lower switches S1’-S4’
As compare to the diode clamped inverter FCMLI don’t require conduction of consecutive switches at a time. This topology focuses more on phase redundancy than line-to-line redundancy as in case of NPCMLI. This allows charging and discharging of particular capacitors and can be incorporated in control systems for balancing various voltage levels.
2.3.2 Features of FCMLI
The voltage rating of each clamping capacitor is same as that of dc bus capacitor. In order to balance the charge and discharge time of capacitor it may take one or more switching sequences. Thus by proper selection of switching sequences one can use this topology for real power conversion.
2.3.3 ADVANTAGES AND DIS ADVANTAGES
• Advantages
Voltage balancing can be possible due to phase redundancy.
Real and reactive power flow can be controlled.
Large numbers of capacitor protect the model from voltage sag.
Model provides more control over he circuit to the user.
• Disadvantages
Control is quite complicated as it’s very difficult to keep eye on each capacitor’s voltage level and also pre-charging of such a large numbers of capacitor is a toilsome work.
Switching sequence and efficiency is poor for real power transmission.
The circuit becomes more complex, bulky and difficult for packing for higher voltage levels.
High switching frequency and losses due to complex control technique which is a major setback while transferring real power.
2.4 CASCADED H-BRIDGE MLI (CHBMLI)
Cascade H-Bridge inverter is the most advanced and widely used inverter due to lower ripple component in the output voltage and also voltage balancing is not a major issue in this topology. This topology came to the knowledge when two researchers Lai and Peng described its various advantages in 1997. Due to its high modularity this topology has a wide range of high power applications. As the voltage level raises the ripple component and harmonics in the output voltage reduces and the waveform becomes more and more close to sinusoidal type along with increase in reactive power. A single H-bridge acts as a single phase inverter. In a cascaded H-bridge inverter such back to back connection of H-bridge generates stepped voltage waveform that has the ability to handle AC system phase balancing. This topology requires numbers of identical voltage sources in order to power individual H-Bridges. The relation between number of sources and voltage level is given by S = 2*n +1; where S is number of sources or bridges and n is the output voltage level.
2.4.1 Operation of CHBMLI
Figure 2.3.a shows a five level cascade H-Bridge inverter which is nothing but the series connection of two single phase H-Bridge inverters. A single phase full bridge model is responsible for producing three voltage levels i.e. +Vdc, 0 and –Vdc. Similarly by joining two H-Bridges the voltage level range at output varies from +2Vdc to -2Vdc. This five level design consists of 2*(n-1) i.e. eight numbers of power electronic switches from S1-S8 and 2 voltage sources. For the voltage output Van= 2Vdc the diagonally placed switches S1, S4 of the first bridge S5, S8 of the second bridge need to be turned, for Van= Vdc the switches S1, S4 and S8 need to be triggered. Similarly for Van=0 no need switches need to be triggered. The switching sequence for Van= -Vdc the switches S7,S6 and S2 need to be triggered and for -2Vdc the switch S3 along with the former switch are triggered simultaneously.
2.4.2 ADVANTAGES AND DISADVANTAGES
• Advantages
Topology provides high degree of modularity of control.
Soft switching method can be implemented to reduce loss.
Simple voltage balancing modulation technique.
Circuit requires less components as compared to other VSI for same voltage levels which gives the circuit a proper layout and requires less cost and time for its manufacture
• Disadvantages
Model requires identical and isolated dc sources which limits its applications.
Communication between multiple full bridges is required for proper synchronization of reference and carrier wave.
3.1 SIMULATION
In this chapter various topologies of three different levels of inverters i.e. 5-level, 7-level and 11-level inverters are compared on the basis certain criterion like of THD, distortion factor numbers of voltage sources circuit complexity etc with the help of MATLAB/SIMULINK software and its results and waveform are shown below. All these models that are represented here were simulated in MATLAB/SIMULINK environment by considering restive load only and are driven by pulse width modulation technique (PWM).
3.2 FIVE LEVEL INVERTERS
Five level inverter topologies discussed in this chapter are driven by PWM technique as with the help of this method the harmonics, ripple in output voltage waveform can be reduced, distortion fact0r can be improved and apart from that this technique is less costly and occupies less memory space. A five level voltage wave form consists of usually less 8 voltage steps in a full cycle, by the relation m= 2*(n-1), of which 7 steps are even whose length in terms of time domain is given by 0.02/m in this case 0.02/8 and rest one step is divided in to two equal halves of size 0.02/2m i.e. 0.02/18. From this steps size the switching time or delay can be calculated which can be further used to get the switching angle and pulse width.
Switching angle = (t/T)*360; t = time delay;
T = time period;
Pulse width in % = (t2-t1)/T *100;
Where t2 – t1 = duration for which a set of switches are tuned on and
T = time period of a cycle
3.2.1 five-level NPCMLI
As in the figure in the chapter two a five level NPCMLI consists of 2*(n-1) numbers of power switches i.e. 8, (n-1)*(n-2) numbers of clamping diodes 12 in this case along with 4 numbers of dc bus capacitor. The circuit has been designed and simulation reports are presented.
Figure 3.2.1 output waveform of 5-level NPC
From the FFT analysis it’s cleared that this waveform rich in odd harmonics with THD of 39.86% with the optimal distortion factor.
Figure3.2.2 Harmonic order of 5-level NPCMLI
3.2.2 five-level FCMLI
Capacitor clamped model is simpler than diode clamped model in terms of circuit complexity and numbers of component. Still a five level FCMLI requires 2*(n-1) numbers of power switches i.e. 8 in this case along with (m-1)*(m-2)/2 i.e. 6 numbers of clamping capacitors along with four dc bus capacitors. The simulation of five-level FCMLI for resistive load is represented below.
Figure 3.2.3 output waveform of five-level FCMLI
In the above figure the irregularity in the output voltage steps due to variation of duty cycle of different switches which results in variation in charging and discharging time of the capacitors in a half cycle which causes voltage unbalancing. The harmonic component in this waveform is very high witnessing 42.65% of THD with lower distortion factor.
Figure 3.2.4 harmonic order of five-level FCMLI
3.2.3 cascaded H-Bridge MLI
The CHBMLI model consists of series connection of 2 full H-Bridges. Each bridges employing 4 power switches and two identical and isolated voltage sources. In comparison to above two mention topologies CHBMLI has significantly less THD i.e. around 28.54% along with higher distortion factor.
Figure 3.2.5 output waveform of CHBMLI
Figure 3.2.6 harmonic order of five-level CHBMLI
3.4 Modified CHB with reduced numbers of switches
This topology is similar to CHB except that this employs comparative lesser number of switches than CHBMLI with nearly same THD and distortion factor as that of CHBMLI for same output voltages. The THD in case of five-level five switches MLI is 29.71%.
Figure 3.2.7 output waveform of five-level Reduced Switched MLI
Figure 3.2.8 harmonics order of 5-level Reduced Switch MLI
3.2.5 Comparison
Table 3.1 comparison of various topologies of five-level inverter
Topology/
Criteria NPCFLI FCFLI CHBFLI CHBRSFLI
Phase switches 8 8 8 5
Close phase diodes 12 0 0 0
DC bus capacitors 4 4 0 0
Voltage sources 1 1 2 2
Balancing capacitors 0 6 0 0
THD % 39.86 42.65 28.54 29.71
From the above comparison table, by considering all the criterions and factors, it can be concluded that five- level Reduced Switched topology is the most suitable model for real life applications. Although it has slightly THD then CHBMLI, still it uses lesser numbers of switches then CHB. Apart from that this topology employs lesser number of pulses which saves the memory spaces and reduces the cost of the inverter.
3.3 SEVEN LEVEL INVERTERS
Seven-level MLI is the next higher level inverter with lesser THD and ripple components than the previous one
3.3.1 Seven-level NPCML
A seven-level NPCMLI consists of 2*(n-1) numbers of power switches i.e. 12, (n-1)*(n-2) numbers of clamping diodes 30 in this case along with 6 numbers of dc bus capacitor. The circuit has been designed and simulation reports are presented.
Figure 3.3.1 seven level NPC inverter
Figure 3.3.2 harmonics order of NPCSLI
From the FFT analysis it’s cleared that this waveform rich in odd harmonics with THD of 37.88% with the optimal distortion factor.
3.3.2 Seven-level FC Inverter
Capacitor clamped model of a seven level FCMLI requires 2*(n-1) numbers of power switches i.e. 12 in this case along with (m-1)*(m-2)/2 i.e. 15 numbers of clamping capacitors along with six dc bus capacitors. The simulation of five-level FCMLI for resistive load is represented below.
Figure 3.3.3 output waveform of FCSLI
In the above figure the irregularity in the output voltage steps due to variation of duty cycle of different switches which results in variation in charging and discharging time of the capacitors in a half cycle which causes voltage unbalancing. The harmonic component in this waveform is very high witnessing 34.05% of THD with lower distortion factor.
Figure 3.3.4 harmonics order if FCSLI
3.3.3 cascaded H-Bridge SLI
The CHBMLI model consists of series connection of 3 full H-Bridges. Each bridges employing 4 power switches and two identical and isolated voltage sources. In comparison to above two mention topologies CHBMLI has significantly less THD i.e. around 21.37 % along with higher distortion factor.
Figure 3.3.5 Output waveform of CHBSLI
Figure 3.3.6 harmonics order of CHBSLI
3.4 Modified CHB with reduced numbers of switches
This topology is similar to CHB except that this employs comparative lesser number of switches than CHBMLI with nearly same THD and distortion factor as that of CHBMLI for same output voltages. The THD in case of five-level five switches MLI is 24.22%.
Figure 3.3.7 output waveform of CHB with Reduced switch
Figure 3.3.8 Harmonics order of Reduced Switched SLI
3.2.5 Comparison
Table 3.1 comparison of various topologies of Seven-level inverter
Topology/
Criteria NPCFLI FCFLI CHBFLI CHBRSFLI
Phase switches 12 12 12 6
Close phase diodes 30 0 0 0
DC bus capacitors 6 6 0 0
Voltage sources 1 1 3 3
Balancing capacitors 0 15 0 0
THD % 37.88 34.05 21.37 24.22
From the above comparison table, by considering all the criterions and factors, it can be concluded that Seven- level Reduced Switched topology is the most suitable model for real life applications. Although it has slightly THD then CHBMLI, still it uses lesser numbers of switches then CHB. Apart from that this topology employs lesser number of pulses which saves the memory spaces and reduces the cost of the inverter.
3.4 ELEVEN-LEVEL INVERTER
3.4.1 Eleven-level NPCML
An Eleven-level NPCMLI consists of 20 power switches, 90 clamping diodes along with 10 numbers of dc bus capacitor. The circuit has been designed and simulation reports are presented.
Figure 3.4.1 voltage waveform of NPCELI
From the FFT analysis it’s cleared that this waveform rich in odd harmonics with THD of 18.21% with the minimal distortion factor
Figure 3.4.2 Harmonic order of NPCELI
. 3.4.2 Eleven-level FC Inverter
Capacitor clamped model of an eleven-level FCMLI requires 20 power switches, along with 45 numbers of clamping capacitors and ten dc bus capacitors. The simulation of eleven-level FCMLI for resistive load is represented below.
In the above figure the irregularity in the output voltage steps due to variation of duty cycle of different switches which results in variation in charging and discharging time of the capacitors in a half cycle which causes voltage unbalancing. The harmonic component in this waveform is very high witnessing 27.93% of THD with lower distortion factor
Figure 3.4.3 voltage waveform of FCELI
Figure 3.4.4 harmonic orders of FCELI
3.4.3 Cascaded H-Bridge ELI
The CHBMLI model consists of series connection of 5 full H-Bridges. Each bridges employing 4 power switches and five identical and isolated voltage sources. In comparison to above two mention topologies CHBMLI has significantly less THD i.e. around 16.12 % along with higher distortion factor.
Figure 3.4.5 voltage waveform of CHBELI
In this case also the THD of cascaded H-Bridge is slightly less than the reduced switched model but if the power switches, cost and numbers of triggering PWM pulses drawn in to consideration then the Reduced switch ELI would be the best suitable inverter for industrial and domestic applications.
Figure 3.5.6 harmonic order of Reduced switched ELI
3.4.4 Modified CHB with reduced numbers of switches
This topology is similar to CHB except that this employs comparative lesser number of switches than CHBMLI with nearly same THD and distortion factor as that of CHBMLI for same output voltages. The THD in case of eleven-level five switches MLI is 24.22%.
Figure 3.4.7 output waveform of ELI with reduced switches
Figure 3.4.8 harmonic order of ELI with reduced switches
3.2.5 Comparison
Table 3.1 comparison of various topologies of Eleven-level inverter
Topology/
Criteria NPCFLI FCFLI CHBFLI CHBRSFLI
Phase switches 20 20 20 8
Close phase diodes 90 0 0 0
DC bus capacitors 10 10 0 0
Voltage sources 1 1 5 5
Balancing capacitors 0 45 0 0
THD % 18.21 27.93 16.12 24.22
5.1 CONCLUSION
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