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Analysis of Phase Noise and Jitter in Ring Oscillators

1).Tripti Kackar, 2).Shruti Suman, 3.)P. K. Ghosh

Abstract-- Voltage controlled oscillators (VCOs) have gain paramount importance in frequency modulation (FM) and pulse modulation (PM) circuits, phase locked loops (PLL), function generators, and frequency synthesizers which are vital for communication circuits. CMOS based ring oscillators have tuning range, tuning gain and phase noise as the important characteristics. The most difficult task is that variation of  pahse due to stochastic  perturbations. Phase noise has been the designer’s primary concerned presently. The effect of oscillator’s noise is one of the most insightful issues in the designing of modern RF elecommunication systems. A low phase noise with minimum power dissipation is rapidly preferred criteria in the voltage controlled ring oscillator (VCRO). A very simple and precise analysis of different phase noise models and their causes is analysed in the paper for ring VCOs configurations. For each case, the flicker and the white noise component of phase noise and jitter are considered which limits the signal. The important elements that determine the phase noise in VCOs are the transistor's flicker noise ( noise), the output power level, and the quality factor (Q). A synchronized relationship among the effective noise components in the oscillatory circuits leads to good agreement for new design insights and improves performance.

   Index Terms-- Ring Oscillators, Voltage Controlled Oscillator (VCO), Voltage Controlled Ring Oscillator (VCRO), Phase noise, jitter.


VOLTAGE controlled oscillators (VCOs) are categorized among the class of oscillators where the frequency of the output oscillation can be varied by the biasing of a controlled voltage signal. They are fundamental electronic modules in the wide sectors of communication. They have variety of applications such as RF transceivers, modulator and

1. Ms. Tripti Kackar is pursuing M.Tech. from Mody University, Lakshmangarh, Rajasthan.( e-mail:  [email protected])

2. Ms. Shruti Suman is working as Assistant Professor in ECE department, Mody University, Lakshmangarh, Rajasthan since 2012.( e-mail: [email protected]).

3. Dr. P. K. Ghosh is currently Head of Department, in ECE department, Mody University, Lakshmangarh, Rajasthan was born in Kolkata, India in 1964. he has more than 30 research papers in Journals of repute and conference proceedings. He is life member of Indian Society for Technical Education (ISTE), New Delhi. His research interests are in the areas of reduced order modelling, VLSI circuits & devices, wireless communications and signal processing.(e-mail:  [email protected])

demodulator, radio frequency identification devices (RFID) transponders [1] medical domains [2] and clock data recovery circuit.Extensive research has been done and is ongoing from the past years for CMOS oscillator’s respectively. Modeling for VCOs is concerned with its instantaneous phase along with the signal amplitude and waveform shape. Consequently, modeling is often done in the phase domain.

This paper provides designers with an overview of phase noise and jitter aspects. The section 2 gives brief information about relationship between phase noise and jitter. Section 3 focuses on describing their impact on system performance, and identifies techniques to minimize them. Section 4 gives conclusion and future scopes. The output expression for VCO can be given by equation (1) as shown:


where,   is frequency  with periodic in   and  and denotes fluctuations in amplitude and phase due to internal and external noise sources. The instantaneous frequency of a VCO is generally modeled as a linear relationship with its instantaneous control voltage as given in equation (2) [3]. Fig. 1 shows that the output phase of the oscillator is the integral of the instantaneous frequency as expressed in equation (3):



where, is the instantaneous frequency of the oscillator or VCO's frequency at time t,  is the quiescent frequency of the oscillator, is called the oscillator sensitivity, or gain. Its units are hertz per volt, is the VCO's output phase,  is the time-domain control input or tuning voltage of the VCO. For analyzing a control system, the Laplace transforms of the above signals are useful; mathematically can be expressed as equation (4) and (5):



Phase noise study of an oscillator considers its transfer function as linear with respect to infinitesimally small input  noise perturbations to output phase. From oscillator theory, two conditions are required to make a feedback system oscillate: the open loop gain must be greater than unity; and total phase shift must be 360° at the frequency of oscillation. Oscillator has positive feedback loop at selected frequency which is of keen interest. It is seen that frequency of such oscillation can be increased by decreasing the number of stages or by altering device dimensions, which often end up disastrously increasing the power consumption. The odd number of stages are well suited for single ended oscillators and will always oscillate  whereas differential configurations can have both odd as well as  even number stages such that one stage does not invert. Such differential even number of stages of are useful for generating quadrature or multiphas outputs [4].


Fig. 1.  Fundamental model of ring VCO

Thus, proper frequency stability is necessary for operation of the oscillator [5]. Frequency Stability is a measure of the degree to which an oscillator maintains the same value of frequency over a given time. Phase noise is the short-term random frequency fluctuations of a signal; is measured in the frequency domain, and is expressed as a ratio of signal power to noise power measured in a 1 Hz bandwidth at a given offset from the desired signal. In other way, it is a measurement of uncertainty in phase of a signal. Both the systemic noise and the random noise contribute to the phase noise of the ring oscillator. The systemic noise such as common-mode supple noise can be avoided by using symmetric architectures, while the influence of the random noise such as thermal noise and flicker noise cannot be easily alleviated. There are various ways of improving phase noise such as increasing the width of the device and minimizing the channel length, which also add the power dissipation and many more. The power spectral density of pink noise increases as frequency is reduced, and at low enough frequencies it dominates Johnson and shot noise.


Phase noise and jitter are different ways of quantifying the same phenomenon but in different domains. Phase noise is the frequency domain representation of random fluctuations in the phase of a waveform. A high voltage swing with improved linearity of delay helps minimizing ring oscillator phase noise. Jitter is a random variation of the signal in time domain and essentially describes how far the signal period shows variation from its ideal value. These occur due to  are identifiable interference signals; due to crosstalk between adjacent signal traces, EMI radiation sources in signal path, substrate noise and switching. For high speed circuits the prime requirement is of optimization of phase noise and jitter. This noise spreads the signal to adjacent frequencies, resulting in noise sidebands. The phase noise is typically expressed in   and represents the amount of signal power at a given sideband or offset frequency from the ideal carrier frequency [6]. Hence jitter is the time domain instability of the signal, usually expressed in picoseconds. There are three regions shown in Fig. 2, the flat region  at large offset frequency is the noise floor. The  region is referred to as the “white frequency” variation region, since it is due to white, or uncorrelated, fluctuations in the period of the oscillator. The behavior in this region is dominated by the thermal noise in the devices of the oscillator circuit.

Fig. 2 Phase noise representation with  flicker noise component for ring VCO

Fig. 3: Calculation of jitter from phase noise

At sufficiently low offset frequencies the flicker noise of devices usually comes into play and the spectrum in this region falls as   [7].

The first step in calculating the equivalent RMS jitter is to obtain the integrated phase noise power over the desired range of frequency i.e., the area of the curve, A. The curve is divides into smaller of individual areas (A1, A2, A3, A4), as shown in Fig. 3 each defined by two data points. Generally speaking, the upper frequency range for the integration should be twice the sampling frequency. The integration of each individual area yields individual power ratios. The individual power ratios are then summed and converted back into dBc. Once the integrated phase noise power is known, the RMS phase jitter in radians is given by the equation as shown below in equation (6) [8].

RMS Phase Jitter ( radians ) =  


and dividing by  converts the jitter in radians to jitter in seconds as given in equation (7):

RMS Phase Jitter (seconds ) =


Although the use of a deep submicron process allows the possibility of higher VCO frequency, it also introduces the problem of a higher 1/f noise. The high  phase noise is due to the poor  device noise in the deep submicron process. Even though the  phase noise corner can be significantly, lowered by improving waveform symmetry [9], the applicability is limited for ring oscillators since it is impossible to get symmetric rising and falling edges. Differential ring oscillators do not have symmetry advantage over single-ended peers since it is the symmetry of the half circuits that matters.


The advantage of differential VCO compared to single-ended VCO is the superior common-mode noise (i.e. power supply and substrate noise) rejection ability. Therefore, the differential VCO is more suitable for modern mixed-signal IC on-chip environment, in which the digital circuitry will generate a substantial amount of power supply and substrate noise. Since the transition of each stage is triggered by the previous stage, at a single time only one stage in the ring is switching and thus contributing jitter[10]. Therefore the jitter analysis for the CMOS inverter is the best way to characterize the capacity of jitter optimization for different semiconductor processes.

According to [11], the phase noise of the differential ring oscillator  has an inverse relationship with the control current and the voltage swing as stated in equation (8):


The total average noise power   in a particular   frequency band can be found by integrating the power spectral density (PSD) as given below in equation (9):



The average noise power  for any random process is expressed as given in equation (10):


 where  is the noise voltage given by equation (11) such as,


Also, switching time   for each cycle is defined in equation (12) as,


Here,  is the load capacitance at the output of each node,  is the power supply voltage and  is the current in the device during operation. Hence, fundamental noise analysis done for ring oscillator yields average noise power ( ) as the function of time constant, delay at each stage and oscillation frequency which can be given by equation (13)  as :


where T is the  oscillation  period, is on-time of the transistor per delay cell,  is the offset frequency of the carrier signal,   is the time constant of the delay cell, and   is the Boltzmann’s constant having value  1.38 x 10-23 J/K.

3.1 Lesson’s Model

An early one-port  model for the phase noise spectrum of oscillators was formulated by D.B Lesson’s [12]. Variations of this model is presently taken for the modeling of phase noise in oscillators reveals relationship between shot noise, power and quality factor . The phase noise can be closely stated as in equation (14) .



where   is the Boltzmann’s constant having value  1.38 x 10-23 J/K,  is the average signal power dissipated, is the absolute temperature,F is fitting parameter for figure of noise, is corner angular frequency between   and  components of flicker noise and  Q is quality function of the oscillator, Δω is frequency offset from the carrier ( Hz) and ωo = carrier frequency (Hz) which is expressed as given by equation (16):


Here in equation (15), this input phase noise spectrum is expected to have two regions. One region is due to the additive white noise, 2FKT/Ps at frequencies around the oscillator frequency. The second region is due to   introduced by parameter variation at low frequencies. This includes both white noise and flicker noise which has a power spectral density inversely proportional to frequency.

When   increases due to decrease in -3db bandwidth results in sharpening of the peak in magnitude response. The analysis of noise in the system can be done by keeping in mind evaluation of noise added at the input, noise current generated due to the sources and thermal actions.

3.2 Razavi’s Model

In Razavi’s model for noise analysis an oscillator is considered as two port LTI feedback system. These oscillators give output phase noise of the ring oscillator in frequency domain with function of average power   as following equations (17) and (18):


In an oscillator with large Q, the required instantaneous change in frequency for given phase shift is smaller, thus giving better frequency stability.

This model adopts LTI approach to model differential CMOS ring oscillators as shown in equation (18).


It is seen that the input and the output nodes of any of the delay stages never reach the balanced state together. Therefore, inverter based ring oscillator never act as a linear amplifier during the transitions. Hence its phase noise can not be analyzed with linearity assumption.

3.3 Hajimiri Model

A more accurate linear time invariant model is  developed by Hajimiri  and Lee [12]; which introduces Impulse sensitivity function to undertake effects of cyclostationarity virtue of noise. Phase change is proportional to change in voltage hence can be written as in equation (19):


where  is the time-varying “proportionality constant” called as impulse sensitivity function. Phase noise depends on the time when the noise current is injected. oscillators has different noise sensitivity at different time instants over the period. It accounts for cyclostationarity through modulated ISFwhich can be shown as equation (20):



 A noise current component   whose frequency is near an integer multiple (n) of the oscillation frequency has the form of equation (21) which further yields simplified equation (22) as follows:




Here,  is the root mean square (RMS) value of the ISF, where  is the total square noise spectral density per Hertz for long channel CMOS transistors, which can be expressed mathematically as in equation (23) [13] :


where ,again   can be expressed as in equation  (24):


But, we know that the linearized bulk charge, surface potential at source and surface potential at the drain plays vital  significant ; therefore, drain source conductance comes into design given by equation (25):


Therefore above equation (26) can be modified as :



Here, with γ=2/3 for MOSFETs in the saturation region and γ varies from 2/3 to 1 as the drain-to source voltage VDS varies from zero to the onset of the saturation. For long-channel MOSFETs in the saturation region, the value can be expressed as given in equation (27):



With the advancement, waveform symmetry is of great importance for minimization of phase noise strongly dependent on the oscillation amplitude. For short channel noise, the linearity criteria for resistance and channel length does not satisfy due to degraded charge carrier mobility; also the   (excess noise factor due to hot electron effect ) observed to be two or three times larger than that of long-channel MOS transistors in saturation. These models for non-linearity, is prescribed to obtain time dependent sensitivity in the oscillators.

Therefore, the dependency of the oscillation frequency on the channel length L is given by following equation (28):



3.4 Demir’s Model

This model is complex, pure mathematical based  and involves  no circuit intuition. This model is non linear, mathematically involved and CAD oriented. It can be described by one dimensional differential equation. Q-factor definition is not utilized throughout analysis. It develops solid foundation of phase noise regardless of operating mechanism. It requires solving of complex differential equations but more accurate. It’s able to predict injection locking behavior of oscillator hence its universal model. Demir’s model represents oscillator by a group of equations in the form as  expressed as equations (29) [14] :


When the oscillator is perturbed by a small perturbation b(t), the output voltage where y(t) is the orbital deviation. Finally the phase noise resulting from the voltage perturbation b(t) can be obtained by solving the following one dimensional differential equation (30):


Here, x(t) is the oscillator’s output voltage. The methods of this model are faster than the traditional brute force Monte Carlo approach of phase noise simulation [15].

3.5 Ham’s Model

This model is recent and contributions in the scenario of phase noise and jitter domains which act as a bridge between conventional and existing  noise theories. It is simple and intuitive model which is valid for both LTI and LTV modeling of phase noise. In this model, concept of  virtual damping  rate is taken  as a  fundamental measure of phase noise[16]. This model is capable to explain up conversion, down conversion of noise in the vicinity of integral multiple of oscillation frequency. Analysis using this not require long simulation time and does not have computational overhead.

Considering that all oscillators start oscillating at the

same time instant, it’s found that the ensemble average over time exhibits exponential damping. If the phase diffusion is due to white noise, the variance of  which signifies the width of the probability distribution is given by equation (31) as :



Here phase diffusion constant ‘D’ is the reciprocal of the exponential time constant in damping of ensemble/time average and is also called as virtual damping rate. For LTV analysis time varying effects are taken in to account for evaluating diffusion constant.


With the scaling of  technology in the recent years, high density of integration and fast speed has posed a serious challenged to the design considerations such as power supply, stability and most importantly phase noise in circuits. The major focus has been laid on low phase noise and low jitter devices. Important VCO phase noise models such as  Lesson’s linear model and Hajimiri’s time-variant model were analyzed. Abidi’s model was studied for the phase noise and jitter process in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation is used for flicker noise. Analysis showed that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current. This analysis aids better understanding of phase and jitter phenomena. Apt minimization of noise distortion in the circuits leads to high performances.


Rezvan Dastanian, Ebrahim Abiri, Mohammad Reza Salehi, Saeed Ghorbani, “A temperature compensated CMOS differential ring oscillator with low power consumption for RFID applications”, International Journal of Engineering & Technology Sciences, Vol .03, No. 1, February 2015, pp. 45-54.


Ahmet Tekin, Mehmet R. Yuce, and Wentai Liu, “Integrated VCOs for Medical Implant Transceivers”, Hindawi Publishing Corporation, 2008,

[3] B.  Razavi, Design of analog CMOS integrated circuits, Tata McGraw - Hill, Third edition, 2001.

[4] Zuow-Zun Chen and Tai-Cheng Lee, “The design and analysis of dual-delay-path ring oscillators”, IEEE Transactions on Circuits and Systems, Vol. 58, No. 3, March 2011, pp. 470 - 478.

[5] Adel S.Sedra and Kenneth C.Smith, Microelectronics Circuits, Theory and Applications, Oxford Publications, Sixth edition, 2013.

[6] James Wilson (2010), "Jitter Attenuation: Choosing the Right Phase-Locked Loop Bandwidth," Silicon Laboratories Inc.

[7] Ulrich L. Rohde (1983),“Digital PLL Frequency Synthesizers Theory and Design”, Prentice-Hall, ISBN 0-13-214239-2, pp. 411-418.

[8] Adnan Gundel (2007), "Low Jitter Phase-Locked Loop Clock Synthesis With Wide Locking Range," New Jersey Institute of Technology, PhD Thesis.

[9] Boris Drakhlis (2001), "Calculate Oscillator Jitter by using Phase-Noise Analysis  Part 2," Microwaves and RF, February 2001, pp. 109.

[10] A. Hajimiri and T. H. Lee (1998), “A general theory of phase noise in electrical oscillators,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 179-194.

[11] J. McNeill (1997), “Jitter in ring oscillators,” IEEE Journal of Solid-State Circuits, vol. 32, pp. 870-879.

[12] Ali Hajimiri and Thomas H. Lee (2003), “The Design of Low Noise Oscillators”,  Kluwer Academic Publishers.

[13] Y. Tsividis (1988), “Operation and Modeling of the MOS Transistor,” McGraw-Hill.

[14] Asad A. Abidi, “Phase noise and jitter in CMOS ring oscillators” IEEE Journal of Solid-State Circuits, Vol. 41, No. 8, August 2006, pp. 1803-1816.

[15] A. Demir, “Phase Noise in Oscillators: DAEs and Colored Noise

Sources”, In Proc. IEEE ICCAD, pp. 170-177, 1998

[16] Donhee Ham, Ali Hajimiri, “Virtual Damping and Einstein Relation

in Oscillators”, IEEE J. Solid-State Circuits, vol. 38, no. 3, March.



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