Essay: Arithmetic and logic functions

UNIT II
ARITHMETIC OPERATIONS
ALU – Addition and subtraction – Multiplication – Division – Floating Point operations – Subword parallelism.
2.1 ALU
Let us discuss about the Arithmetic and logic functions:
The arithmetic operations are addition, subtraction, multiplication and division. The logic operations are AND, OR, NOT, EXOR.
The different arithmetic and logic functions are realized and integrated in an ALU as shown in the below Figure.
4-bit adder/subtractor showing ALU operations
The 4-bit adder/subtractor is used to add 2’s complement numbers X and Y, where x0, x1, x2, x3 and y0, y1, y2, y3 are the sign bits.
In this case, the carry out bit C3 is not part of the answer.
Overflow obviously occurs if the sign of the result is different.
Therefore, a circuit to detect overflow can be added to the n-bit adder by implementing the logic expression
In order to perform the subtraction operation X- Y on 2’s complement number X and Y, we form the 2’s complement of Y and add to it to X.
The logic circuit network shown in above figure can be used to perform either addition or subtraction based on the value applied to the Add/Sub input control line.
This line is set to 0 for addition, applying 7 vector unchanged to one of the adder inputs along with a carry in signal C0, of 0.
When the Add/Sub control line is set to 1, the Y vector is l’s complemented by the XOR gate and C0 is set to 1 to complete the 2’s complementation of Y.
An XOR gate can be added to detect the overflow condition Cn ⊕ Cn- 1.
2.2 Addition and subtraction
Let us see the Add/Subtract Rule
1.Choose the number with the smaller exponent and shift its mantissa right a number of steps equal to the difference in exponents.
2.Set the exponent of the result equal to the larger exponent.
3.Perform addition/subtraction on the mantissa and determine the sign of the result.
4.Normalize the resulting value, if necessary.
Multiplication and division are somewhat easier than addition and subtraction, in that no alignment of mantissa is needed.
Here we shall see the diagrammatic design of 4-bit binary adder/subtractor:
4-bit adder/subtractor
The 4-bit adder/subtractor is used to add 2’s complement numbers X and Y, where x0, x1, x2, x3 and y0, y1, y2, y3 are the sign bits.
In this case, the carry out bit is not part of the answer.
Overflow obviously occurs if the sign of the result is different.
Therefore, a circuit to detect overflow can be added to the n-bit adder by complementing the logic expression.
In order to perform the subtraction operations X – Y on 2’s complement number X and Y we form the 2’s complement of Y and add to it to X.
The logic circuit network shown in above figure can be used to perform either addition or subtraction based on the value applied to the Add/Sub input control line.
This line is set to O for addition, applying Y vector unchanged to one of the adder inputs along with a carry in signal C0, of O.
When the Add/Sub control line is set to 1, the Y vector is 1’s complemented by the XOR gate and C0 is set to 1 to complete the 2’s complementation of Y.
Let us discuss about the Hardware implementation of addition and subtraction :
The logical operations are simple to implement using combinational circuitry.
They require only independent boolean operations on individual bit position of the operands.
Full adder:
A full adder is a combinational circuit that forms the arithmetic sum of three inputs and two outputs.
Two of the input variable denoted by X and Y represent two significant bits to be added, the third input C representing carry from the previous lower significants position.
The two outputs are designated by symbols S for sum and C for carry.
Full Adder
Arithmetic overflow occurs in case of 2’s complement addition when the signs of the two operands are same.
In case of n bit adder the overflow obviously occurs if the sign of the result is different. Therefore, a circuit to detect overflow can be added to n bit adder by implementing the logic expression.
Overflow: x n-1 y n-1 S n-1 + xn-1 y n-1 Sn-1
Logic for addition of binary vector:
Parallel Adder
The logic circuit network can be used to perform either addition or subtraction based on the value applied to the add/sub input control line.
This line is set to O for addition, applying the Y vector unchanged to one of the adder input along with the carry in signal, adder input along with the carry in signal, C0 of 0.
When the add/sub control line is set to 1.
The Y vector is l’s complemental by the XOR gates and C0 set to 1 to complete the 2’s complement of Y in subtraction.
Binary addition-subtraction logic network
DESIGN OF FAST ADDRESS
Using n bit Ripple carry adder and addition/subtraction logic networks some delays occurred. The delay through a network of logic gates depends on the integrated circuit electronic technology.
Two approaches can be taken to reduces delay in adders.
(i)To use fastest possible electronic technology.
(ii)To use an augmented logic gate network structure.
A number of design techniques have been used to implement high speed adders carry look ahead addition is used for last propagation of carry signals as well as variations on the basic network structure.
Carry Look-Ahead Addition
A fast adder circuit must speed up the generation of the carry signals the logic expressions for Si (Sum) and Ci + 1 (Carry out) of Stage i are,
Si = xi ⊕ yi ⊕ ci
and
Ci + 1 = xiyi + xici + yici.
Factoring the second equation in to
Ci + 1 = xiyi + (xi + yi)Ci
we can write
Ci + 1 = Gi + PiCi
where Gi = xi yi and Pi = xi + yi
The expression Gi and pi are called the generate and propagate functions for stage i, if the generate function for stage i is equal to 1, then Ci + 1 = 1, independent of the input carry C.
This occurs when both Xi and Yi are 1.
The propagate function means that an input carry will produce an output carry when either Xi is 1 or Yi is 1.
All Gi and pi functions can be formed independently and in parallel in one logic gate delay after X and Y vectors are applied to the i/p of an n-bit adder.
Each bit stage contains an AND gate to form Gi an OR gate to form Pi and a three input XOR gate to form Si.
A simpler circuit can be derived by observing that an adequate propagate function can be realized as Pi = Xi + Yi which differs from Pi = Xi + Yi only when Xi = Yi = 1.
Then, using a cascade of two input XOR functions, the basic cell Bi can be used in each bit stage.
Carry Look Ahead Adder
Expanding Ci in terms of i – 1 subscripted variables and substituting in to the Ci + 1 expression,
Ci + 1 = Gi + PiGi-1 + PiPi-1 Ci-1
In case of a 4 bit adder, the carries can be implemented as
C1 = G0 + P0C0
C2 = G1 + P1G0 + P1P0C0
C3 = G2 + P2G1 + P2P1G0 + P2P1P0C0
C4 = G3 + P3G3 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0
The complete 4 bit adder is shown in following Figure.
4-bit carry look ahead Adder
Higher-level generate and propagate function.
By using higher level block generate and propagate function, it is possible to us the lookahead approach to develop carries C4, C3, Cl2,…, in parallel in a higher level carry lookahead circuit.
Gate delays when higher level block generate and propagate functions are used.
The delay in developing carries produced by the carry look ahead circuits is two gate delay more than delay needed to develop and and hence totally 5 gate delays. A 64 bit adder can be built from hout of the 16 bit adders with additional carry lookahead logic circuits.
Let us discuss about the Ripple carry adder:
(i)If an n-bit ripple carry adder is used in addition/subtraction unit it may have too much delay in developing its sum and carry.
(ii)The delay through a network of logic gates depends on the integrates circuit electronic technology used in fabrication network. This delay encountered in the disadvantage in the ripple carry adder.