Abstract–Adders are an integral part of modern day processors, Carry select adders (CSLA) being one of the commonly used efficient adder. But this efficiency comes with the cost of a larger area and higher power dissipation. Over time, scaling the transistor sizes has reduced the area but due to the CMOS logic style designing, the circuit still remains complex. Hence in this work a gate-level modification method called Gate Diffusion Input (GDI) is proposed in order to reduce the power and area of the CSLA. The standard CMOS CSLA is compared with GDI-logic CSLA using Virtuoso?? Spectre?? Circuit Simulator and power, delay and Power Delay Product (PDP) are tabulated using 45nm Technology node. The analysis shows that GDI-based logic style is simple in terms of transistor count and provides better performance compared to the standard CMOS logic style.
1. Introduction
In VLSI design; power, delay and area are issues designers have to deal with while designing for portable devices. The length and width scaling of transistors is one such method of reducing the area and power dissipation. It has helped in reducing the area of transistors but retains the design complexity due to the CMOS design methodology. Since scaling transistor widths and lengths below a certain level introduces other effects, the system performance is degraded with scaling. Hence the design methodology at the transistor level has to be modified to obtain further improvements in performance.
In digital adder circuits, the propagation delay of the carry limits the speed of the addition process. Each block generates a sum only after receiving the carry from the previous block and a new carry is passed to the next block. Hence CSLA architecture alleviates the carry propagation delay by generating partial sums and carry readily assuming Cin=0 and Cin=1 using Ripple Carry Adders (RCA). A Multiplexer (MUX) then selects the final carry and sum outputs. Generally all these blocks are implemented in standard CMOS which makes the design complex and consumes large area and power.
In this work each block of the SQRT-CSLA is implemented using GDI-logic. GDI-Logic uses a simple inverter but with different input configuration to implement basic gates and then develop different blocks using the GDI-blocks. GDI-Logic is discussed in Section 3.
Section 2 describes the basic SQRT-CSLA architecture and the analysis methodology. Section 4 shows the proposed implementation of the CSLA using the GDI-Logic. Simulation results and comparison between the logic styles is discussed in section 5. Section 6 discusses the future scope of the work.
2. Basic SQRT-CSLA Architecture
The basic 16-bit SQRT-CSLA is shown in the Fig.1.The CSLA is divided into four groups to simplify the analysis process. There are 2 sets of RCA in each group which generates the sum and carry, one set assuming Cin=0 and the other Cin=1. The detailed division is as follows:
Group2: It has two set of 2-bit RCA and one 6:3 MUX (Fig.2a).
Group3: It has two set of 3-bit RCA and one 8:4 MUX (Fig.2b).
Group4: It has two set of 4-bit RCA and one 10:5 MUX (Fig.2c).
Group5: It has two set of 5-bit RCA and one 12:6 MUX (Fig.2d).
Fig.1: Basic 16-bit SQRT-CSLA [2]
(a) (b)
(c)
(d)
Fig.2: CSLA divided into (a)group2 (b)group3 (c)group4 (d) group5
As seen from the figures the CMOS implementations of all these blocks are complex with respect to the transistor count. Hence the GDI-Logic is used in this work instead of CMOS-Logic, to reduce the transistor count and thereby reducing the average power.
3. GDI-Logic Design
The GDI-Logic uses a simple inverter cell as shown in Fig.3 to implement different Boolean Functions. The GDI cell contains three inputs: G (common gate input of nMOS and pMOS), P (input to the source/drain of pMOS), and N (input to the source/drain of nMOS) [1]. The bulk connections are similar to that in standard CMOS Logic.
Fig:3 Basic GDI-Cell
Table 1: Different input configurations to be applied to the GDI-Cell.
Table 1 shows the different input configurations to be applied to the GDI-cell to implement various Boolean Functions. It can be seen how the GDI-Logic is capable of implementing the standard CMOS design in a compact way. The number of transistor reduces drastically in GDI-Logic providing lower power consumption and less area utilization. These GDI-cells were used to develop the basic blocks of the SQRT-CSLA and then compared with the standard CMOS-Logic counterparts.
4. Proposed Implementation
Initially the basic gates AND and OR were designed using GDI-Logic by giving the input configurations as discussed in Table1 to the inverter. Using these basic gates XOR gate was implemented. Similarly the XOR and AND gates were used to implement the 1-bit Half-Adder(HA) which was used for designing the 1-bit Full-Adder(FA). These GDI-logic based circuits were compared with standard CMOS circuits with respect to power, delay and transistor count. The Table 2 shows the comparison of GDI-logic circuits with CMOS-logic circuits.
Blocks CMOS-Logic GDI-Logic
Transistor Count Average Power (W) Transistor Count Average Power (W)
AND 6 350.4n 2 40.45n
OR 6 216.4n 2 40.22n
XOR 22 1.211u 6 215.3n
HA 28 1.38u 16* 765n*
FA 62 2.714u 42* 1.931u*
MUX 20 669.9n* 6 268.4n*
The above data shows how GDI-Logic design simplifies the complexity in CMOS-Logic style with reduced power consumption. Due to the drain and source diffusion being used as inputs, swing restoration becomes an issue in GDI-Logic. This is solved by adding buffers between the basic blocks.
5. Simulation Results
The simulations schematic design and simulations were carried in using Virtuoso?? Spectre?? Circuit Simulator using 45nm Technology node. The average power was calculated using the Calculator tool in Spectre?? simulator. The supply voltage used for the simulation is 1V and all the inputs have a rise-time (TR) and fall-time (TF) of 10psec respectively. The table shows the comparison of the various groups of a CSLA in standard CMOS and GDI-Logic in terms of average power and the transistor count.
Blocks CMOS-Logic GDI-Logic
Transistor Count Average Power (W) Transistor Count Average Power (W)
Group2 308 14.2u 186 9.54u
Group3 452 22.68u 276 13.92u
Group4 596 27.34u 366 16.2u
Group5 740 32.94u 456 20.93u
The comparison shows that the transistor count reduces by nearly 38% in GDI-logic compared to CMOS-logic. Similarly the average power is reduced by 30%.
6. Conclusion and Future Scope
In this work the basic CSLA has been implemented using the low-power GDI-Logic in 45nm
Technology node. The simulation results and comparison showed how the GDI-Logic was
better than CMOS-logic in terms of power and transistor count.
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