Essay: FPGA based Jpeg encoder

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  • FPGA based Jpeg encoder
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Compression is playing a vital role in data transfer. Hence, Digital camera uses JPEG standard to compress the captured image data from sensors so as to reduce the storage requirements. Because, Photos capture from digital camera are big in size, so it take more time to upload such photos on web. Some time connection speed creates bottle neck on uploading these photos. Best way is to save such photos by .jpg extension and share on the web. Sometimes, while copying the original data, it may not fit in pen drive or memory stick but zip data could easy fit in pen /memory stick. More data one can put in pen drive due to compression. The paper focuses on realization of a JPEG encoder by designing and implementing on an FPGA board. The processing system is coupled with DCT and entropy encoding to form a JPEG encoder.
Keywords-JPEG, DCT, FPGA.
The use of digital technology in everyday life and specialized applications continues to increase with each passing year. In particular, the use of digital imagery continues to grow as the technology to create this media becomes cheaper and more accessible. In addition, technological advances in many fields, such as robotics, medicine and defense, continue to increase the need for digital imagery. As more applications demand higher resolution imagery and rely on it for critical information, the need to store this data efficiently while maintaining data integrity is predominant. To illustrate this need, consider a standard smart phone featuring an 8 megapixel camera. If an image is taken in monochrome with 8 bits of precision for each pixel, this requires 8 MB of memory prior to compression. While this does not seem like much, considering hard drives are available with terabytes of storage space, consider a video sequence captured using the same camera at a rate of 30 frames per second. This requires a total of 240 MB of space per second and over 14 GB of space for a single minute. Clearly, storing images in a raw format is not feasible, especially when considering applications which use color images or higher resolution cameras.
A still digital image can be compressed using lossless compression or lossy compression. No loss of data occurs when the image is compressed using a lossless compression technique. Some information is lost while compressing an image using lossy compression techniques. This is acceptable, as the human visual system (HVS) can tolerate significant losses. Many applications require the higher compression ratios only possible using lossy compression. Compression of an image is achieved by exploiting its statistical properties. Redundancy and irrelevancy reduction are two key principles used in the compression of images. Redundancy reduction aims at removing duplication from the source. Irrelevancy reduction omits parts of the signal that will not be noticed by the HVS. Image compression research aims at reducing the redundancy and irrelevancy as much as possible so as to reduce the number of bits needed to represent an image.
The Joint Photographic Experts Group (JPEG) was established in 1992 as the still image compression standard by the International Standards Organization(ISO) and the International Electro-Technical Commission (IEC).JPEG compresses color and gray scale images of natural or real world scenes. JPEG coders suffer from performance losses at lower bit rates due to the underlying discrete cosine transform (DCT) used for the compression of images.
Table 1. Literature Survey on [3] [4] [5] [6] [7] [8].
Year Author No. of bit planes
Gate count +
Power (mW)
2003 Chung Jr. Lian et. al. 8 50.00 19,000 +
13kb 115 TSMC 0.35um 1P4M
2005 Grzegorz Pastuzak 10 66.00 ~ 8,500
— Altera Stratix
2006 Yijun Li, Magdy Bayoumi — 75.00 5,200 +
6Kb 410 AMS 0.35um CMOS
2002 Tien-Wie Hsieh et. al. 16 43.47 27,069
22 Altera
2004 Amit Kumar Gupta, et. al. 16 51.70 631 — APEX20KE
2009 Kishor Sarawadekar et. al. 18 67.28 12,952+
21 Kb 330 XC2V1000
Figure 1 shows the main block diagram of all encoding processes based on the DCT.
Figure 1. Block Diagram
1. Source Image data
In the encoding process the input component’s samples are grouped into 8 x 8 blocks, and each block is transformed by the forward DCT (FDCT) into a set of 64 values referred to as DCT coefficients. One of these values is referred to as the DC coefficient and the other 63 as the AC coefficients.
2. DCT
Apply Discrete Cosine Transform to each block separately. For DCT-based processes, two alternative sample precisions are specified: either 8 bits or 12 bits per sample. There are four distinct modes of operation under which the various coding processes are defined:
a) Sequential DCT-based,
b) Progressive DCT-based,
c) Lossless DCT-based, and
d) Hierarchical DCT-based.
3. Quantization
In this step, less important DCT coefficients are removed.
Each of the 64 coefficients is then quantized using one of 64 corresponding values from a quantization table. No default values for quantization tables are specified in this Specification; applications may specify values which customize picture quality for their particular image characteristics, display devices, and viewing conditions.
4. Encoding Process
Here, Huffman encoding is used. After quantization, the DC coefficient and the 63 AC coefficients are prepared for entropy encoding.
Xilinx CORE generator is used in project. The CORE Generator System is a design tool that delivers parameterized cores optimized for Xilinx?? FPGAs. It provides you with a catalog of ready-made functions ranging in complexity from simple arithmetic operators such as adders, accumulators, and multipliers, to system-level building blocks such as filters, transforms, FIFOs, and memories. A core cannot be remotely accessed from within a project. Cores must reside inside the project directory in order to be accessible to the project. Coregen is not available for CPLD devices. It is not possible to copy cores from one project to another. You will need to generate new cores if you import a design from another design environment. CoreGen cores are often optimized for a particular device family. To avoid errors in implementation after changing to a new device family, most cores need to be regenerated for the new family.
Figure 2. Top level RTL for JPEG Encoder
JPEG encoder with 77 Input and outputs are shown in Figure 2. The JPEG Encoder implementation on Vertex 5 infers 13185 gate count. This design works on a frequency 29.046MHz.
Figure 3 : RTL for JPEG Encoder
The device utilization for JPEG Encoder is as reflected in synthesise report and it shown in figure 3, which is part of various levels of RTL.Out of 5120 Slices 5056 are used in this design i.e. 98% utilization. Number of Slice Flip Flops are 4866 out of 10240.Number of 4 input LUTs: 8427 out of 10240 .
Implementations of JPEG on FPGA platform using different methodologies was carried out. The extensive literature survey explored that different authors have implemented JPEG using minimum 631 to maximum 27,069 gate count and memory elements. These implementations works on minimum 43 MHz to 75 MHz at Xilinx, Altera etc. FPGA platforms. Study of different image interchange format, image header format and design implementation flow of Coregen is carried out. The synthesis is carried out on Vertex 5 platform. The JPEG Encoder implementation on Vertex 5 infers 13185 gate count. This design works on a frequency 29.046MHz.
[1] Design and implementation of an embedded NIOS II system for JPEG2000 TIER II encoding by John M. McNichols.
[2] FPGA implementation of a parallel EBCOT TIER -1 encoder that preserves encoding efficiency.
[3] Chung – Jr. Lian, Kua – Fu Chen, Hong – Hui Chen, and Liang – Chen, ‘Analysis and Architecture 3.Design of Block Coding Engine for EBCOT in JPEG 2000,’ IEEE Transactions on Circuits and Systems for Video Technology, Vol.1, No.3, pp. 219 – 230, March, 2003.
[4].Grzegorz Pastuzak, ‘A High-Performance Architecture for Embedded Block Coding in JPEG 2000,’ IEEE Transactions Circuits and Systems for Video Technology, Vol. 15, No. 9, pp. 1182’1191, September, 2005.
[5].Yijun Li, Magdy Bayoumi, ‘A Three-Level Parallel High-Speed Low-Power Architecture for EBCOT of JPEG2000,’ IEEE Transactions Circuits and Systems for Video Technology, Vol. 16, No. 9, pp. 1153’1163, September, 2006.
[6].Tien-Wie Hsieh and Youn-Long Lin, ‘A Low-Power and High Performance EBCOT Architecture of JPEG2000 Encoding,’ IEEE Symposium on Circuits and Systems, Vol. 1, pp. 773’776, May, 2002.
[7].Amit Kumar Gupta, David Taubman and Saied Nooshabadi, ‘High-Speed VLSI Architecture for Bit Plane Encoder of JPEG2000,’ 47’th IEEE Midwest Symposium on Circuits and Systems, Vol. 2, pp. 25-28, 2004.
[8].Kishor Sarawadekar and Swapna Banerjee ,’A high speed bit plane coder for JPEG 2000 and its FPGA implementation,’ 17th European Signal Processing Conference (EUSIPCO 2009) Glasgow, Scotland, August 24-28, 2009.

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