Essay: THROUGHSILICON VIA (TSVs) IN 3D INTEGRATED CIRCUIT

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PROGRESS AND CHALLENGES OF POSITIONING AND NUMBERING OF THROUGHSILICON VIA (TSVs) IN 3D INTEGRATED CIRCUIT
Abstract—In 3-D Integrated circuit the dies are stacked vertically by identifying the location, numbering and position of TSVs. By using TSVs, optimization is done in wire length, area and power. The TSVs are also used for the power distribution, inter networks connections etc. The size of thermal TSVs depends on the implementation and maximum temperature of the 3D ICs. The TSVs are fabricated before or during the bounding of wires. The block-level integration requires TSVs to be placed between placements blocks. TSV may require aligned dead-space regions on adjacent dies. A 3D design has more packing densities therefore it has higher power densities. Sophisticated thermal management research is going on to resolve these potential problems. The Location or positioning of TSVs in 3D integrated circuit is a major task for designing. The position of TSVs is done using Keep out Zone. The method used for solving those problems requires new stochastic techniques.
Keywords: Through Silicon Via (TSVs), Keep Out Zone(KOZ), Wire length, Dead Space
I. INTRODUCTION
The Through Silicon via(TSV) is considered to be the future design style in semiconductor industries. In 3-D Integrated circuit(IC) the dies are stacked vertically by identifying the location, numbering and position of TSVs. Now a day’s 3D Integrated circuit technology has become viable and improves the functionality of the electronic devices with the presence of TSVs. By using TSVs optimization is possible such as wire length, area and power.
The TSVs are used for the power distribution in the 3D IC stack are called power TSVs, While TSVs used for inter networks called signal TSVs. The size of the power TSV is larger than the signal TSVs in order to reduce the voltage drop and also to meet current density requirements. Whereas the size of thermal TSVs depends on the implementation and maximum temperature of the3D ICs. Approximately the thermal vias consume 10% to 20% of the chip area for maximum temperature reduction of 47%[1]. Figure1: 3D Integrated Circuit
TSVs are classified using the via-first and via-last technologies. In the first approach, the TSVs are fabricated before or during the bounding of wires. While in the via-latest approach, the TSVs are fabricated after the bonding of wires.The dimension of TSVs usually varies from 1”m to 90 ”m for both the technologies.
Figure 2: Length and position of TSVs.
Review of classic and recent placement algorithms suggests a dichotomy between approaches that either: (a) heuristically minimize potentially irrelevant objective function (b) devise elaborate problem-specific minimization heuristics for more relevant objective functions. Smoothness and convexity of the objective functions typically enable efficient minimization [1]. If either characteristic is not present in the objective function, one can modify and restrict the objective to special values of parameters to provide the missing properties. Thus, it is the modification step that deserves most attention. In this paper, we approximate the 3D IC placement with the presents of TSV positioning and numbering. This allows the use of Evolutionary algorithms for minimization and, for standard numerical methods, translates into a tradeoff between solution, quality and speed.
II. PROBLEM DISCRIPTION
A. 3D IC integration:
There are two methods of IC integration. Namely: block level and gate level integration. The main requirement of block level integration is that Through Silicon via (TSVs) should be placed in between the placement blocks. Therefore, the Through Silicon via overhead must be limited, which favors block level integration when compared with gate level integration. Depending on the die stacking technique, TSV may require aligned dead-space regions on adjacent dies. This is referred to as the dead space alignment problem.
B. Thermal management:
A 3-Dimensional Integrated circuit (IC) design has more packing densities. So, it has higher power densities. Sophisticated thermal management has developed to resolve these potential problems. Some of the common techniques used are: thermal aware block placement [2] to spread higher power blocks and (ii) insertion of thermal TSVs which to increase the vertical thermal conductivity of a 3D IC [2].The maximal temperature for the 3D IC can be minimized if, for each die, the TSV area in any given (2D) is proportional to the lumped power consumption of this and all overlapping bins from dies.
C. TSV positioning and numbering:
The through Silicon via (TSVs) is pivotal in the future Integrated Circuit (IC) technologies. In 3D Integrated circuit the stacked layers are connected only through TSVs and not by ordinary wires. The two major tasks in designing the IC is that SoC (System on a Chip) and PoP (Package on Package) [3].
Folding and stacking based transformation is used to connect from 2D to 3D design and graph layer assignment will be a good option. In order to remove overlap density, recurring function can be utilized.
Stochastic techniques like genetic algorithm, frog leaping algorithm simulated annealing, memetic algorithms can be efficiently used for EDA tool TSV placement, simplifies TSV designs and obtains best optimized wire length and also suits for better TSV numbering and positioning. Also Swarm intelligence can be effectively utilized.
TSV Number estimation given by Objective function
TSV(e) ‘ (( log ‘ vi ‘V exp (zi / ” ) + log ‘ vi ‘V exp (- zi / ” )) (1)
The ” value can be set to 0.01.
The TSVs circuit is represented as hyper graph H= (V1, E2) (2)
Where, V1 is a vertices and E1 is a hyper graph edges.
V1={V1,V2,”Vn} (3)
E1={e1,e2,”en} (4)
The placement region Rij is a scaled layers which is represented as S. Where device is placed on layer Zi’ {1,2,’S} and centre is placed at,
(xi,yi) ‘ Rij (5)
The Location or positioning of TSVs in 3D integrated circuit is a major task for designing. The position of TSVs is done using the technique called Keep out Zone (KOZ). There is some challenges in TSV fabrication such as, while TSV fabrication it causes tensile mechanical stress around TSVs because of the mismatch in the Coefficients of Thermal Expansion between silicon and copper (CTE). The Keep Out Zone is nothing but the area surrounding the each TSV from which the logic cells must ‘keep out” so that the mechanical stress caused by the TSVs can be reduced to the certain extent. In order to know the size of Keep out Zone (KOZ), the magnitude of mechanical stress caused by TSVs was studied and analyzed accordingly.
Figure 3: Size and positioning of TSVs
III. CONSTRAINTS AND REQUIREMENTS:
The main constraints and requirements of TSV positioning and numbering is as follows: The simple complexity of wiring and achieves better optimal wire length. By optimizing the TSV placement, leads to some advantages of low cost, higher reliability and obtains better TSV position and also reduces the TSV count.
There are three different types of TSVs such as: Power TSVs, Ground TSVs and Signal TSVs. Because of these different kinds of TSVs, the complexity increases. The TSVs are assigned using different algorithms namely: 3D minimum spanning Tree algorithm, Minimum cost flowed based algorithm, Neighborhood scaled based algorithm. The keep Out Zone and routing congestions are very important processes in TSV positioning and numbering.
The method used for solving those problems by using (a) mobility variation modeling, (b) Evolutionary algorithms for optimization, (c) layer by layer HPM algorithm.
A. Mobility variation modeling:
The TSV-induced stress is taken into account for simulated annealing (SA), an analytical model of TSV stress-induced carrier mobility variation was proposed in [4]. The Carrier mobility change depends on not only applied stress, but also orientation between the stress and a transistor channel. The effect from multiple TSV’s can be combined by using linear super-position.
B. Evolutionary Algorithm-Simulated Annealing:
The simulated annealing (SA) is one of the evolutionary algorithms used for optimization of area and wire-length. The pseudo code of SA is as follows:
It starts from a state s0 and continues to either a maximum of kmax steps or until a state with energy of emin or less is found. In the process, the call neighbor(s) should generate a randomly chosen neighbor of a given state s; the call random (0, 1) should pick and return a value in the range [0, 1), uniformly at random. The annealing schedule is defined by the call temperature(r), which should yield the temperature to use, given the fraction r of the time budget that has been expended so far.
Let s = s0
For k = 0 through kmax (exclusive):
T ‘ temperature(k ‘ kmax)
Pick a random neighbour, snew ‘ neighbour(s)
If P(E(s), E(snew), T) > random(0, 1), move to the new state:s ‘ snew
Output: the final state s
In order to apply the SA method to a specific problem, one must specify the following parameters: the state space, the energy (goal) function E(), the candidate generator procedure neighbor(), the acceptance probability function P(), and the annealing schedule temperature() AND initial temperature . These choices can have a significant impact on the method’s effectiveness [5].
Figure 4: Flow of Simulated Annealing
C. Layer by layer HPM algorithm:
The half-perimeter wire length (HPWL) model is commonly used because it is reasonably accurate and efficiently calculated. The bounding box of a net with p pins is the smallest rectangle that encloses the pin locations [6]. The wire length is estimated as half the perimeter of the bounding box. For two-and three-pin nets (70-80% of all nets in most modern designs), this is exactly the same as the rectilinear Steiner minimum tree (RSMT) cost. The objective function of wire length is given asW(obj).
W(obj).= ‘e ‘ E (1+re). (WL(e) +”TSV.TSV(e)) (6)
The Objective function depends on placement (xi,yi,zi) and its weighted sum of wirelength WL(e) and number of TSV(e) overall nets.
The weight of (1+re) reflects the criticality of the net e and is related to performance optimization. The unweighted wire-length is represented by setting re to0.
The weight is able to model the thermal effects by relating it to the thermal resistance, electronic capacitance, and switching activity of net(e).
The wire-length is estimated using Half perimeter wire-length.
Wire-length WL(e) given by ,
WL(e) = ((max vi ‘e{xi } ‘min vi ‘e{xi }) + (max vi ‘e{yi } ‘min vi ‘e{yi }) ) (7)
And TSV(e) modelled by equation,
TSV(e)= max vi ‘e{zi } ‘min vi ‘e{zi } (8)
IV. CONCLUSION
The TSV modeling and design of 3D integrated circuit is one of the biggest challenges facing in the semiconductor industry. These challenges can be addressed using stochastic techniques because of the discrete nature of the objective functions. The scope of this area is that at levels of Physical design TSV optimization can be performed which reduces area, power and temperature of Three Dimensional Integrated Circuits.
REFERENCES:
[1] D. H. Kim, K. Athikulwongse, and S. K. Lim, ‘A study of through silicon via impact on the 3D stacked IC layout,’ in Proc. IEEE Int.Conf. Computer-Aided Design, San Jose, CA, Nov. 2’5 2009, pp. 674’680.
[2] K. H. Lu et al., ‘Thermo-mechanical reliability of 3-D ICs containing through silicon vias,’ in IEEE Electronic Components and Technology Conf., San Diego, CA, May 26’29 2009, pp. 630’634.
[3] J. Cong, G. Luo, J. Wei, and Y. Zhang. Thermal-Aware 3D IC Placement ViaTransformation. In Proc. Asia and South PacificDesign Automation Conf., 2007.
[4] D. H. Kim, S. Mukhopadhyay, and S. K. Lim. TSV-aware
Interconnect Length and Power Prediction for 3D Stacked ICs. In Proc. IEEE Int. Interconnect Technology Conference, 2009.
[5] J. Cong, G. Luo, and Y. Shi, ‘Thermal-aware cell and through-silicon via co-placement for 3D ICs,’ in Proc. 48th Des.Autom. Conf., 2011, pp. 670’675.
[6] R. Hentschke, G. Flach, F. Pinto, and R. Reis, ‘3D-vias aware quadratic placement for 3D VLSI circuits,’ in Proc. IEEE Comput. Soc. Annu.Symp. VLSI, Mar. 2007, pp. 67’72.
[7] L. Congying, Z. Huanping, and Y. Xinfeng, ‘Particle swarm optimization algorithm for quadratic assignment problem,’ in Proc. IEEE Int. Conf.Comput. Sci. Netw. Technol., vol. 3. Dec. 2011, pp. 1728’1731.
[8] M.K. Hsu, Y.W. Chang, and V. Balabanov, ‘TSV-aware analytical placement for 3D IC design’, in DAC, June 2011, pp. 664-669.
[9] J. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich, ‘GORDIAN: VLSI placement by quadratic programming and slicing optimization,’IEEE Trans. Computer-Aided Design, vol. 10, pp. 356’365, Mar. 1991.
[10] H. Eisenmann and F. M. Johannes, ‘Generic global placement and floorplanning,’in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 1998.
[11] Mitsuo Gen, Runwei Cheng, ‘Genetic Algorithms And Engineering Design’, John Wiley & Sons,vol-4,pp : 202-203 ,dec 1997.
[12] E. Beyne and et al. Through-Silicon Via and Die Stacking Technologies for Microsystems-integration.In Proc. IEEE Int. Electron Devices Meeting, 2008.
[13] J. W. Joyner, P. Zarkesh-Ha, J. A. Davis, and J. D. Meindl.A Three-Dimensional Stochastic Wire-Length Distribution for Variable Separation of Strata. In Proc. IEEE Int. Interconnect Technology Conference, 2000.
[14] G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, ‘Multilevel hypergraph partitioning: applications in VLSI domain,’ IEEE Trans. on VLSI Systems, vol. 7, no. 1, pp. 69’79, Mar. 1999.
[15] M. Pan, N. Viswanathan, and C. Chu, ‘An ef’cient and effective detailed placement algorithm,’ in Proc. of IEEE/ACM ICCAD, 2005, pp. 48’55.
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[17] Bazargan K, Kastner R, Sarrafzadeh M ‘Simulated annealing and greedy placement methods for Reconfigurable computing systems’. IEEE Workshop on Rapid System Prototyping.Paris France, 2014: 38-43.
[18] J. Cong and M. Xie, ‘A robust mixed-size legalization and detailed placement algorithm,’ IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 8, pp. 1349-1362, Aug. 2014.
[19] D.W. Jepsen and C. D. Gellat, Jr, ‘Macro placement by Monte Carlo annealing,’inProc. Int. Conf. Computer Design, Nov. 1983, pp. 495’498.
[20] C. H. Reilly, ‘Properties of synthetic optimization problems,’ in Proc. Winter Simul. Conf., 1988, pp. 617’621.

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