3.1 Sequential logic
In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on the sequence of past inputs. This is in contrast to combinational logic whose output is a function of only the present input.
Synchronous sequential circuit
A synchronous sequential circuit is a system whose behavior can be defined from the knowledge of its signals at discrete instants of time.
Present state and next state
The information stored in the memory elements at any given time defines the present state of sequential circuit. The present state and the external inputs determine the outputs and the next state of the sequential circuits.
Secondary variables
The delay elements provide a short term memory for the sequential circuit. The present state and next state variables in asynchronous sequential circuits are called secondary variables.
3.2 SR, JK, D and T flip flops
SR Flip-Flop
The SR flip-flop also known as a SR Latch can be considered as one of the most basic sequential logic circuit possible. This simple flip-flop is basically a one-bit memory bistable device that has two inputs, one will "SET" the device (meaning the output = "1"), and is labelled S and another will "RESET" the device (meaning the output = "0"), labelled R.
Then the SR description stands for "Set-Reset".
The reset input resets the flip-flop back to its original state with an output Q that will be either at a logic level "1" or logic "0" depending upon this set/reset condition.
A basic NAND gate SR flip-flop circuit provides feedback from both of its outputs back to its opposing inputs and is commonly used in memory circuits to store a single data bit.
Then the SR flip-flop actually has three inputs, Set, Reset and its current output Q relating to its current state or history.
The term "Flip-flop" relates to the actual operation of the device as it can be "flipped" into one logic Set state or "flopped" back into the opposing logic Reset state.
Circuit of SR flip-flop
State diagram
Truth Table
NAND Gate
S
R
Q(t + 1)
A
B
Y
0
0
Indeterminate
0
0
1
0
1
Set
0
1
1
1
0
Reset
1
0
1
1
1
NC
1
1
0
Characteristics table
S
R
Q
0
0
Q
0
1
0
1
1
0
1
0
1
1
*
*
SR flip – flop using NOR gates
The SR latch with two cross coupled NOR gates is shown.
NOR Based SR Latch
For a NOR gate, if any input is 1 output is 0 and output is 1, only when all the inputs are 0.
Case 1: Let S = 0 and R = 0. Let us assume that present state Qn = 0 and The inputs of NOR gate 1 is 0 and 1, therefore its output Qn + 1 = 0. This (Qn + 1 = 0) is fedback to NOR gate 2 input thereby producing 1 as its output. So.
Now let us assume that Qn = 1 and . This Qn= 1 is applied to the input of NOR gate 2 and therefore the output Qn + 1 is 0. This is fed to input of NOR gate 1 there by producing a output Qn + 1 = 1.
So far the condition S = 0 and R = 0, the next state of the latch is just the present state.
Case 2: The second input condition is S = 0 and R = 1. The 1 at the reset (R) inputs forces output of NOR gate 1 low. ie., Qn + 1 = 1. This makes both the inputs of NOR gate 2 "0" and its output Thus S = 0 and R = 1 condition reset the flip flop.
Case 3: The third input condition is S = 1 and R = 0. The 1 at the SET (S) input forces output of NOR gate 2 low i.e., Now both the inputs of gate 1 are 0 and thus its output Qn + 1 = 1. Hence S = 1 and R = 0 condition set the flip – flop.
Case 4: When S = 1 and R = 1 outputs of both the NOR gates are 0. This violates the fact that the outputs Qn + 1 andare the complements of each other. So both inputs should not be applied simultaneously.
Truth Table
Inputs
Outputs
Remarks
S
R
Qn + 1
0
0
Qn
No Change
0
1
0
1
Reset
1
0
1
0
Set
1
1
X
X
Indeterminate
Let us convert a SR flip – flop into JK flip – flop.
Solution
Step 1: Draw the characteristic table of JK flip – flop and excitation table of SR flip – flop.
Characteristic Table
Excitation Table
Qn
J
K
Qn + 1
S
R
0
0
0
0
0
X
0
0
1
0
0
X
0
1
0
1
1
0
0
1
1
1
1
0
1
0
0
1
X
0
1
0
1
0
0
1
1
1
0
1
X
0
1
1
1
0
0
1
Step 2: Obtain simplified expression for S and R interms of J,K and Qn using K-map.
Step 3: Draw the circuit of JK flip-flop.
Drawback of SR flipflop
The major drawback is that output becomes not defined whenever both inputs S = R = 1.
JK flip – flop
The simple JK flip flop is the most widely used of all the flip-flop designs and is considered to be a universal flip-flop circuit. The sequential operation of the JK flip flop is exactly the same as for the previous SR flip-flop with the same "Set" and "Reset" inputs.
The difference in this time is that the "JK flip flop" has no invalid or forbidden input states of the SR Latch even when S and R are both at logic "1".
The JK flip flop is basically a gated SR Flip-flop with the addition of a clock input circuitry that prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to logic level "1".
Due to this additional clocked input, a JK flip-flop has four possible input combinations, "logic 1″, "logic 0″, "no change" and "toggle". The symbol for a JK flip flop is similar to that of an SR bistable Latch.
Truth table
Inputs
Outputs
Remarks
CLK
J
K
Qn+l
0
0
0
Qn
No change
0
0
I
Qn
No change
0
1
0
Qn
No change
0
1
1
Qn
No change
1
0
0
Qn
No change
1
0
1
0
1
Reset
1
1
0
1
0
Set
1
1
1
Qn
Toggle
State diagram
Characteristic Equation
Excitation table
Qn
Qn + 1
J
K
0
0
0
X
0
1
1
X
X => Don't care
1
0
X
1
1
1
X
0
State diagram and state table for ’JK’ flip-flops
Q
J
K
Q(t + 1)
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
0
D Flip Flop – Characteristic Table
Here is the characteristic table for a D flip flop.
D
Q
Q+
Operation
0
0
0
Reset
0
1
0
Reset
1
0
1
Set
1
1
1
Set
The D flip flop characteristic table has 3 columns.
• The first column is the value of D, a control input.
• The second column is the current state, that is the current value being output by Q.
• The third column is the next state, that is the value of Q at the next positive edge. It is labelled with Q and the superscript, + (the plus sign).
Sometimes, the current state is written as Q(t) which means the value of Q at the current time(t) and the next state is written as Q(t + 1) which means the value of Q at the next clock edge. However, it is usually written as Q+.
The characteristic table is unusual because the second column isn't really an input, it's an output. The third column is really the same output but just the output at a future time.
The D flip flop has two possible values. When D = 0, the flip flop does a reset. A reset means that the output, Q is set to 0. When D = 1, the flip flop does a set which means the output Q is set to 1.
Working of flip flop
When the clock is not at a positive edge, the flip flop ignores D. However at the positive edge, it reads in the value D and based on D, it updates the value of Q (and of course Q').
There is some small amount of delay while it reads in the control input (from D) and the output.
In fact, the "D" in D flip flop stands for "delay". It basically means that the "D" value is not read immediately but only at the next positive clock edge.
'D' flip-flop
Q
D
Q(t + 1)
0
0
0
0
1
1
1
0
0
1
1
1
T Flip Flop – Characteristic Table
Here is the characteristic table for a T flip flop.
T
Q
Q+
Operation
0
0
0
Hold
0
1
1
Hold
1
0
1
Toggle
1
1
0
Toggle
The T flip flop characteristic table has 3 columns.
• The first column is the value of T, a control input.
• The second column is the current state, that is the current value being output by Q.
• The third column is the next state, that is the value of Q at the next positive edge.
It is labelled with Q and the superscript, + (the plus sign).
The T flip flop has two possible values:
• When T = 0, the flip flop does a hold. A hold means that the output, Q is kept the same as it was before the clock edge.
• When T = 1, the flip flop does a toggle which means the output Q is negated after the clock edge compared to the value before the clock edge.
Thus in a T flip flop, we can either maintain the current state's value for another cycle.
Applications of Flip-Flop:
1) Used as Memory Element.
2) Used as Delay Element.
3) Data Transfer.
4) Frequency Division and Counting.
Difference between a latch and flip flop:
•The output of a latch changes immediately when its inputs changes.
•The output of a flip flop changes only when its clock pulse is active and its input changes.
Problem
Here we consider that a sequential circuit has two JK flip flops A and B, two inputs X and Y and one output Z. The equations are Let us draw the logic diagram and state table.
Solution
P.S.
Next State
Output Z
XY = 00
XY = 01
XY = 10
XY = 11
XY = 00
XY = 01
XY = 10
XY = 11
A
B
A
B
A
B
A
B
A
B
0
0
1
0
0
0
1
1
0
1
0
0
0
0
0
1
0
1
0
1
1
0
1
1
1
0
0
0
1
0
1
0
1
0
0
0
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
Let us design a sequential circuit with the four flip flops A, B, C and D. The next states of B, C and D are equal to the present states of A, B and C respectively. The next state of A is equal to the EX-OR of the present states of C and D.
Solution
Present State
Next State
FF Inputs
D
C
B
A
D
C
B
A
JD
KD
JC
KC
JB
Kb
JA
Ka
0
0
0
0
0
0
0
0
0
X
0
X
0
X
0
X
0
0
0
1
0
0
1
0
0
X
0
X
1
X
X
1
0
0
1
0
0
1
0
0
0
X
1
X
X
1
0
X
0
0
1
1
0
1
1
0
1
X
1
X
X
0
X
1
0
1
0
0
1
0
0
1
1
X
X
1
0
X
1
X
0
1
0
1
1
0
1
1
1
X
X
1
1
X
X
0
0
1
1
0
1
1
0
1
1
X
X
0
X
1
1
X
0
1
1
1
1
1
1
1
1
X
X
0
X
0
X
0
1
0
0
0
0
0
0
1
X
1
0
X
0
X
1
0
1
0
0
1
0
0
1
1
X
1
0
X
1
X
X
0
1
0
1
0
0
1
0
1
X
1
1
X
X
1
1
X
1
0
1
1
0
1
1
1
X
1
1
X
X
0
X
0
1
1
0
0
1
0
0
0
X
0
X
1
0
X
0
X
1
1
0
1
1
0
1
0
X
0
X
1
1
X
X
X
1
1
1
0
1
1
0
0
X
0
X
0
X
1
0
X
1
1
1
1
1
1
1
0
X
0
X
0
X
0
X
1
K – map