3.10 Design of Synchronous counters – State diagram, State table, State minimization, State assignment, Excitation table and maps, Circuit implementation
The procedure to design a synchronous counter is listed here.
• Obtain the truth table of the logic sequence for intended counter to be designed. Alternatively obtain the state diagram of the counter.
• Determine the number and type of flip-flop to be used.
• From the excitation table of the flip-flop, determine the next state logic.
• From the output state, use Karnaugh map for simplification to derive the circuit output functions and the flip-flop output functions.
• Draw the logic circuit diagram.
• Simulate the circuit using software.
• Build the circuit.
3.10.1 State diagram
A state represents the status of the flip flops in a sequential circuit. If there are n flip flops then the circuit can have 2n possible states.
State diagram is the graphical representation of the information available in a state table. In state diagram, a state is represented by a circle and the transitions between states are indicated by directed lines connecting the circles.
In addition to graphical symbols, tables or equations, flip-flops can also be represented graphically by a state diagram.
In this diagram, a state is represented by a circle and the transition between states is indicated by directed lines (or arcs) connecting the circles. An example of a state diagram is shown in figure.
State diagram
3.10.2 State table
The state table representation of a sequential circuit consists of three sections labelled present state, next state and output.
The present state designates the state of flip-flops before the occurrence of a clock pulse. The next state shows the states of flip-flops after the clock pulse and the output section lists the value of the output variables during the present state.
A state table gives the time sequence of inputs, outputs and flip-flop states. The table consists of four sections labelled present state, next state, input and output.
3.10.3 State minimization
A partition consists of one or more blocks, where each block comprises a subset of states that may be equivalent but the states in a given block are definitely not equivalent to the states in other blocks.
State Minimization through Partitioning:
Form an initial partition (P1) that includes all states.
Form a second partition (P2) by separating the states into two blocks based upon their output values.
Form a third partition (P3) by separating the states into blocks corresponding to the next state values.
Continue partitioning until two successive partitions are the same (i.e. PN-1 = PN).
All states in any one block are equivalent.
Equivalent states can be combined into a single state.
3.10.4 State assignment
The cost of the combinational circuit of a sequential circuit can be reduced by using the known simplification methods for combinational circuits.
State assignment procedures are concerned with methods for assigning binary values to states in such a way as to reduce the cost of combinational circuit that drives the flip – flops.
Techniques used for state assignment:
i) Shared row state assignment
ii) One hot state assignment
3.10.5 Excitation table and Maps
A synchronous decade counter will count from zero to nine and repeat the sequence.
Since there are ten states, four JK flip-flops are required. The truth tables of present and next state for the decade counter are shown in figure.
State diagram of synchronous decade counter
Truth table and state table of synchronous decade counter
Karnaugh maps of J0 and K0
Karnaugh maps of J1 and K1
Karnaugh maps of J2 and K2
Karnaugh maps of J3 and K3
3.10.6 Circuit implementation
Based on the results obtained from the Karnaugh maps, the circuit design of synchronous decade counter is shown in figure.
Synchronous decade counter designed using JK flip-flop
3.11 Modulo–n counter
Designing synchronous MOD 50 counter:
If the number of flip-flops required is n, then
2n >= 50 i.e., n = 6 Since 26 = 64.
Designing synchronous MOD 25 counter:
If the number of flip – flops required is n, then
2n > = 25ie. n = 5 since 25 = 32.
Modulo-6 Counter:
Let E → Counting enabled.
Present State
Next State
Stable
Output
E
X3
X2
X1
X+3
X+2
X+1
Yes/No
Z
0
0
0
0
0
0
1
Yes
0
0
0
0
1
0
0
1
Yes
0
0
0
1
0
0
1
0
Yes
0
0
0
1
1
0
1
1
Yes
0
0
1
0
0
1
0
1
Yes
0
0
1
0
1
1
0
1
Yes
0
0
1
1
0
1
1
0
Yes
0
0
1
1
1
0
0
0
No
0
Present State
Next State
Stable
Output
E
X3
X2
X1
X+3
X+2
X+1
Yes/No
Z
1
0
0
0
0
0
1
No
0
1
0
0
1
0
1
0
No
0
1
0
1
0
0
1
1
No
0
1
0
1
1
1
0
0
No
0
1
1
0
0
1
0
1
No
0
1
1
0
1
1
1
0
No
0
1
1
1
0
0
0
0
No
1
1
1
1
1
0
0
0
No
0
K-Map Representation:
Mod 7 counter using D Flip-flop:
A modulo – 7 ripple counter is constructed using D flip flops without the NAND gate. This counter functions as a Modulo – 8 binary counter. The presence of NAND gate alters the sequence as follows.
1.The NAND gate output is connected to CLEAR (CLR) inputs of all flip-flops. As long as NAND gate output is HIGH, It will have no effect on counter. When the NAND gate output goes low it will clear all flip-flops and the counter immediately goes to 000 state.
2.The outputs of the counter QA, QB, Qc are given as inputs to the NAND gate. The output of NAND gate goes low whenever QA = QB = Qc=1. This condition will occur when the counter goes from 110 state to 111 state. The low at the NAND gate output will clear the counter to the 000 state.
3.Therefore the counting sequence is → 001 → 010 → 011 → 100 → 101 → 110 → 000 →
7 counter using D Flip-flop
3.12 Registers
3.12.1 Shift registers
A register capable of shifting its binary information in one or both directions from state to state within the register or into or out of the register upon application of clock pulses is called a shift register.
A register that is capable of shifting data, one bit at a time is called a shift register. One of the uses of a shift register is to convert between serial and parallel interfaces.
This is useful as many circuits work on groups of bits in parallel, but serial interfaces are simpler to construct.
Shift registers can be used as simple delay circuits and also as pulse extenders. A serial shift register consists of a chain of flip-flops connected in cascade with the output of one flip-flop being connected to the input of its neighbor.
The operation of the shift register is synchronous; thus each flip-flop is connected to a common clock.
D flip-flops forms the simplest type of shift-registers. The basic data movements possible within a four-bit shift register is shown in figure.
Timing diagram of shift register
The types of shift registers are:
1)Serial In Serial Out (SISO)
2)Serial In Parallel Out (SIPO)
3)Parallel In Serial Out (PISO)
4)Parallel In Parallel Out (PIPO)
Serial-In, Serial-Out :
Destructive Readouts
In destructive readout – each datum is lost once it has been shifted out of the right-most bit.
These are the simplest kind of shift register. The data string is presented at 'Data In', and is shifted right one stage each time 'Data Advance' is brought high.
At each advance, the bit on the far left (i.e. 'Data In') is shifted into the first flip-flop's output. The bit on the far right (i.e. 'Data Out' ) is shifted out and lost.
Non-destructive readout
Non-destructive readout can be achieved if another input line is added – the Read/Write Control.
When this is high (i.e. write) then the shift register behaves as normal, advancing the input data one place for every clock cycle and data can be lost from the end of the register.
However, when the R/W control is set low (i. e. read), any data shifted out of the register at the right becomes the next input at the left and is kept in the system.
Therefore, as long as the R/W control is set low, no data can be lost from the system.
Serial-In, Parallel-Out
This configuration allows conversion from serial to parallel format.
Data are input serially and once the data has been input, it may be either read off at each output simultaneously or it can be shifted out and replaced.
Parallel-In, Serial-Out
This configuration has the data input in parallel format. To write the data to the register, the Write/Shift control line must be held LOW.
To shift the data, the W/S control line is brought HIGH and the registers are clocked.
As long as the number of clock cycles is not more than the length of the data-string, the Data Output, Q, will be the parallel data read off in order.
Parallel-In, Parallel-Out
This kind of shift register takes the data from the parallel inputs (D0-D3) and shifts it to the corresponding output (Q0-Q3) when the registers are clocked.
It can be used as a kind of 'history ' retaining old information as the input in another part of the system until ready for new information,where upon the registers are clocked and the new data are 'let through'.
3.12.2 Universal shift registers
Today, there are many high speed bi-directional "universal" type Shift Registers available such as the TTL 74LS194, 74LS195 or the CMOS 4035 which are available as 4-bit multi-function devices that can be used in either serial-to-serial, left shifting, right shifting, serial-to-parallel, parallel-to-serial or as a parallel-to-parallel multi-function data register, hence the name "Universal".
These universal shift registers can perform any combination of parallel and serial input to output operations but require additional inputs to specify desired function and to pre-load and reset the device. A commonly used universal shift register is the TTL 74LS194.
4-bit Universal Shift Register 74LS194
Universal shift registers are very useful digital devices. They can be configured to respond to operations that require some form of temporary memory storage or for the delay of information such as the SISO or PIPO configuration modes or transfer data from one point to another in either a serial or parallel format.
Universal shift registers are frequently used in arithmetic operations to shift data to the left or right for multiplication or division.
3.12.3 Shift register counters – Ring counter
A shift register can also be used as a counter. A shift register with the serial output connection back to the serial input is called Shift register counter.
There are 2 types of shift Register counters are:
i) Ring counter
ii) Johnson counter
Ring counter:
A ring counter is a circular shift register with only one flip flop being set at any particular time, all others are cleared.
A ring counter is a counter that counts up and when it reaches the last number that is designed to count up , it will reset itself back to the first number.
For example, a ring counter that is designed using 3 JK Flip Flops will count starting from 001 to 010 to 100 and back to 001. It will repeat itself in a 'Ring'
Johnson counter:
The Johnson counter is a K-bit switch-tail ring counter with 2k decoding gates to provide outputs for 2 k timing signals
A Johnson counter is a special case of shift register where, the output from the last stage is inverted and fed back as input to the first stage.
A pattern of bits equal in length to the shift register thus circulates indefinitely.
These counters are sometimes called "walking ring" counters
Used in specialist applications including those similar to the decade counter, digital to analogue conversion, etc.and thus the name Ring Counter.
3.12.4 Shift counters
A synchronous counter that consists of clocked flip-flops are arranged as a shift register. Data is propagated from left to right (or from right to left) between the flip-flops by the application of a clock or count pulse.
Counting is achieved by setting the contents of the shift register to logic 0 (or logic 1) and loading the leftmost (rightmost) flip-flop with a logic 1 (logic 0).
An m-bit counter which has m flip-flops will then require m clock pulses to shift this 1 (or 0) to the rightmost (or leftmost) flip-flop.
The position in the register of the 1 (or 0) thus acts as a count of the number of pulses received since the application of the load.
The counter may be made to count continuously by arranging such that the output of the rightmost (leftmost) flip-flop sets the input of the leftmost (rightmost) flip-flop. The counter is then known as a ring counter.
3.13 Sequence generators
It is nothing but a digital logic circuit whose purpose is to produce a prescribed sequence of outputs. Each output will be one of a number of symbols.
The sequence may be of indefinite length or of predetermined fixed length. A binary counter is a special type of sequence generator.
Sequence generators are useful in a wide variety of coding and control applications.