“DC-DC Converter”;
CHAPTER-3
DC-DC Converter
3.1 Introduction
Modern electronic systems require high quality, small, lightweight, reliable, and efficient power supplies. Linear power regulators, whose principle of operation is based on a voltage or current divider, are inefficient. They are limited to output voltages smaller than the input voltage. Also, their power density is low because they require low-frequency (50 or 60 Hz) line transformers and filters. Linear regulators can, however, provide a very high quality output voltage. Their main area of application is at low power levels as low drop-out voltage (LDO) regulators. Electronic devices in linear regulators operate in their active (linear) modes. At higher power levels, switching regulators are used. Switching regulators use power electronic semiconductor switches in on and off states. Since there is a small power loss in those states (low voltage across a switch in the on state, zero current through a switch in the off state), switching regulators can achieve high energy conversion efficiencies. Modern power electronic switches can operate at high frequencies. The higher the operating frequency, the smaller and lighter the transformers, filter inductors, and capacitors. In addition, dynamic characteristics of converters improve with increasing operating frequencies. The bandwidth of a control loop is usually determined by the corner frequency of the output filter. Therefore, high operating frequencies allow for achieving a faster dynamic response to rapid changes in the load current and/or the input voltage. High-frequency electronic power processors are used in dc–dc power conversion. The functions of dc–dc converters are:
• To convert a dc input voltage VS into a dc output voltage VO;
• To regulate the dc output voltage against load and line variations;
• To reduce the ac voltage ripple on the dc output voltage below the required level;
• To provide isolation between the input source and the load;
• To protect supplied system & input source from EMI;
• To satisfy various international and national safety standards.
The dc–dc converters can be divided into two main types: hard-switching pulse width modulated (PWM) converters, and resonant and soft-switching converters. This chapter deals with the former type of dc–dc converters. The PWM converters have been very popular for the last three decades. They are widely used at all power levels. Topologies and properties of PWM converters are well understood and described in literature. Advantages of PWM converters include low component count, high effficiency, constant frequency operation, relatively simple control and commercial availability of integrated circuit controllers, and ability to achieve high conversion ratios for both step-down and step-up application. A disadvantage of PWM dc–dc converters is that PWM rectangular voltage and current waveforms cause turn-on and turn-off losses in semiconductor devices which limit practical operating frequencies to a megahertz range. Rectangular waveforms also inherently generate EMI.
This chapter starts from a section on dc choppers which are used primarily in dc drives. The output voltage of dc choppers is controlled by adjusting the on time of a switch which in turn adjusts the width of a voltage pulse at the output. This is so called pulse-width modulation (PWM) control. The dc choppers with additional filtering components form PWM dc–dc converters. Four basic dc–dc converter topologies are presented in Sections 3.3–3.6: buck, boost, buck–boost, and C`uk converters. Popular isolated versions of these converters are also discussed. Operation of converters is explained under ideal component and semiconductor device assumptions. Section 3.7 discusses effects of non-idealities in PWM converters. Section 3.8 presents topologies for increased efficiency at low output voltage and for bidirectional power flow. Section 3.9 reviews control principles of PWM dc–dc converters. Two main control schemes, voltage-mode control and current-mode control, are described. Summary of application areas of PWM dc–dc converters is given in Section 3.10. Finally, a list of modern textbooks on power electronics is provided. These books are excellent resources for deeper exploration of the area of dc–dc power conversion.
3.2 DC Choppers
A step-down dc chopper with a resistive load is shown in Fig. 3.1a. It is a series connection of a dc input voltage source VS, controllable switch S, and load resistance R. In most cases, switch S has a unidirectional voltage blocking capabilities and unidirectional current conduction capabilities. Power electronic switches are usually implemented with power MOSFETs, IGBTs, MCTs, power BJTs, or GTOs. If an antiparallel diode is used or embedded in a switch, a switch exhibits a bidirectional current conduction property. Figure 3.1b depicts waveforms in a step-down chopper. The switch is being operated with a duty ratio D defined as a ratio of the switch on time to the sum of the on the off times. For a constant frequency operation, where T=1/f is the period of the switching frequency f. The average value of the output voltage isand can be regulated by adjusting duty ratio D.
(a) (b)
Figure 3.1: DC chopper with resistive load (a) Schematic (b) output voltage waveform
The average output voltage is always smaller than the input voltage, hence, the name of the converter. The dc step-down choppers are commonly used in dc drives. In such a case, the load is presented as a series combination of inductance L, resistance R, and back emf E as shown in Fig. 3.2a. To provide a path for a continuous inductor current flow when the switch is in the off state, an anti parallel diode D must be connected across the load. Since the chopper of Fig. 3.2a provides a positive voltage and a positive current to the load, it is called a first-quadrant chopper. The load voltage and current are graphed in Fig. 3.2b under assumptions that the load current never reaches zero and the load time constant τ = L/R is much greater than the period T. Average values of the output voltage and current can be adjusted by changing the duty ratio D.
(a) (b)
Figure 3.2: DC chopper with RLE load (a) circuit diagram (b) waveforms.
Figure 3.3: The dc step-up chopper
The dc choppers can also provide peak output voltages higher than the input voltage. Such a step-up configuration is presented in Fig. 3.3. It consists of dc input source VS , inductor L connected in series with the source, switch S connecting the inductor to ground, and a series combination of diode D and load. If the switch operates with a duty ratio D, the output voltage is a series of pulses of duration (1−D)T and amplitude VS/(1 − D). Neglecting losses, the average value of the output voltage is VS. To obtain an average value of the output voltage greater than VS, a capacitor must be connected in parallel with the load. This results in a topology of a boost dc–dc converter that is described in Section 3.4.
3.3 Step-down (Buck) Converter
3.3.1 Basic Converter
The step-down dc–dc converter, commonly known as a buck converter, is shown in Fig. 3.4a. It consists of dc input voltage source VS , controlled switch S, diode D, filter inductor L, filter capacitor C, and load resistance R. Typical waveforms in the converter are shown in Fig. 3.4b under assumption that the inductor current is always positive. It can be seen from the circuit that when the switch S is commanded to the on state, the diode D is reverse biased. When the switch S is off, the diode conducts to support an uninterrupted current in the inductor.
The relationship among the input voltage, output voltage, and the switch duty ratio D can be derived, for instance, from the inductor voltage VL waveform (see Fig. 3.4b). According to Faraday’s law, the inductor volt–second product over a period of steady-state operation is zero. For the buck converter.
Eq 3.1
Hence, the dc voltage transfer function, defined as the ratio of the output voltage to the input voltage, is
Eq 3.2
It can be seen from Eq. 3.4 that output voltage is always smaller than input voltage.
Figure 3.4: Buck converter (a) circuit diagram (b) waveforms.
The dc–dc converters can operate in two distinct modes with respect to the inductor current iL. Figure 3.4b depicts the CCM in which the inductor current is always greater than zero. When the average value of the input current is low (high R) and/or the switching frequency f is low, the converter may enter the discontinuous conduction mode (DCM). In the DCM, the inductor current is zero during a portion of the switching period. The CCM is preferred for high efficiency and good utilization of semiconductor switches and passive components. The DCM may be used in applications with special control requirements; since the dynamic order of the converter is reduced. It is uncommon to mix these two operating modes because of different control algorithms. For the buck converter, the value of the filter inductance that determines the boundary between CCM and DCM is given by
Eq 3.3
For typical values of D = 0.5, R = 10_, and f = 100 kHz, the boundary is Lb =25μH. For L > Lb, the converter operates in the CCM. The filter inductor current iL in the CCM consists of a dc component IO with a superimposed triangular ac component.
Almost all of this ac component flows through the filter capacitor as a current ic . Current ic causes a small voltage ripple across the dc output voltage VO. To limit the peak-to-peak value of the ripple voltage below certain value Vr , the filter capacitance C must be greater than
Eq 3.4
At D = 0.5, Vr /VO = 1%, L = 25μH, and f = 100 kHz, the minimum capacitance is Cmin = 25μF. Equations 3.5 and 3.6 are the key design equations for the buck converter. The input and output dc voltages (hence, the duty ratio D), and the range of load resistance R are usually determined by preliminary specifications. The designer needs to determine values of passive components L and C, and of the switching frequency f. The value of the filter inductor L is calculated from the CCM/DCM condition using Eq. 3.5. The value of the filter capacitor C is obtained from the voltage ripple condition Eq. 3.6. For the compactness and low conduction losses of a converter, it is desirable to use small passive components. Equations 3.5 and 3.6 show that it can be accomplished by using a high switching frequency f. The switching frequency is limited, however, by the type of semiconductor switches used and by switching losses. It should be also noted that values of L and C may be altered by effects of parasitic components in the converter, especially by the equivalent series resistance of the capacitor.
3.3.2 Transformer Versions of Buck Converter
In many dc power supplies, a galvanic isolation between the dc or ac input and the dc output is required for safety and reliability. An economical mean of achieving such isolation is to employ a transformer version of a dc–dc converter. High-frequency transformers are of a small size and weight and provide high efficiency. Their turn’s ratio can be used to additionally adjust the output voltage level. Among buck-derived dc–dc converters, the most popular are: forward converter, push–pull converter, half-bridge converter, and full-bridge converter.
A. Forward Converter
The circuit diagram of a forward converter is depicted in Fig. 3.5. When the switch S is on, diode D1 conducts and diode D2 is off. The energy is transferred from the input, through the transformer, to the output filter. When the switch is off, the state of diodes D1 and D2 is reversed. The dc voltage transfer function of the forward converter is
Eq 3.5
where n = N1/N2 Eq 3.6
In the forward converter, the energy-transfer current flows through the transformer in one direction. Hence, an additional winding with diode D3 is needed to bring the magnetizing current of the transformer to zero. This prevents transformer saturation. The turns ratio N1/N3 should be selected in such a way that the magnetizing current decreases to zero during a fraction of the time interval when the switch is off.
Figure 3.5: Forward converter.
Equations 3.5 and 3.6 can be used to design the filter components. The forward converter is very popular for low power applications. For medium power levels, converters with bidirectional transformer excitation (push–pull, half-bridge, and full-bridge) are preferred due to better utilization of magnetic components.
B. Push–Pull Converter
The PWM dc–dc push–pull converter is shown in Fig. 3.6. The switches S1 and S2 operate shifted in phase by T/2 with the same duty ratio D. The duty ratio must be smaller than 0.5. When switch S1 is on, diode D1 conducts and diode D2 is off. Diode states are reversed when switch S2 is on. When both controllable switches are off, the diodes are on and share equally the filter inductor current. The dc voltage transfer function of the push–pull converter is
Eq 3.7
where n = N1/N2. The boundary value of the filter inductor is
Eq 3.8
Figure 3.6: Push-pull converter.
The filter capacitor can be obtained from
Eq 3.9
C. Half-bridge Converter
Figure 3.7 shows the dc–dc half-bridge converter. The operation of the PWM half-bridge converter is similar to that of the push–pull converter. In comparison to the push–pull converter, the primary of the transformer is simplified at the expense of two voltage-sharing input capacitors. The half-bridge converter dc voltage transfer function
Eq 3.10
where D ≤ 0.5. Equations 3.9 and 3.10 apply to the filter components.
Figure 3.7; Half-bridge converter.
D. Full-bridge Converter
Comparing the PWM dc–dc full-bridge converter of Fig. 3.8 to the half-bridge converter, it can be seen that the input capacitors have been replaced by two controllable switches. The controllable switches are operated in pairs. When S1 and S4 are on, voltage VS is applied to the primary of the transformer and diode D1 conducts, With S2 and S3 on, there is voltage −VS across the primary transformer and diode D2 is on.
Figure 3.8: Full-bridge converter.
With all controllable switches off, both diodes conduct, similarly as in the push–pull and half-bridge converters. The dc voltage transfer function of the full-bridge converter is
Eq 3.11
where D ≤ 0.5. Values of filter components can be obtained from Eqs. 3.9 and 3.10. It should be stressed that the full-bridge topology is a very versatile one. With different control algorithms, it is very popular in dc–ac conversion (square-wave and PWM single-phase inverters). It is also used in four-quadrant dc drives.
3.4 Step-up (Boost) Converter
Figure 3.9a depicts a step-up or a PWM boost converter. It is comprised of dc input voltage source VS , boost inductor L, controlled switch S, diode D, filter capacitor C, and load resistance R. The converter waveforms in the CCM are presented in Fig. 3.9b. When the switch S is in the on state, the current in the boost inductor increases linearly. The diode D is off at the time. When the switch S is turned off, the energy stored in the inductor is released through the diode to the input RC circuit. Using the Faraday’s law for the boost inductor
Eq 3.12
from which the dc voltage transfer function turns out to be
Eq 3.13
As the name of the converter suggests, the output voltage is always greater than the input voltage. The boost converter operates in the CCM for L > Lb where
Eq 3.14
For D = 0.5, R = 10_, and f = 100 kHz, the boundary value of the inductance is Lb = 6.25μH. As shown in Fig. 3.9b, the current supplied to the output RC circuit is discontinuous. Thus, a larger filter capacitor is required in comparison to that in the buck derived converters to limit the output voltage ripple.
Figure 3.9: Boost converter (a) circuit diagram (b) waveforms.
The filter capacitor must provide the output dc current to the load when the diode D is off. The minimum value of the filter capacitance that results in the voltage ripple Vr is given by
Eq 3.15
At D = 0.5, Vr /VO = 1%, R = 10_, and f = 100 kHz, the minimum capacitance for the boost converter is Cmin = 50μF. The boost converter does not have a popular transformer (isolated) version.
3.5 Buck–Boost Converter
3.5.1 Basic Converter
A non-isolated (transformerless) topology of the buck–boost converter is shown in Fig. 3.10a. The converter consists of dc input voltage source VS , controlled switch S, inductor L, diode D, filter capacitor C, and load resistance R. With the switch on, the inductor current increases while the diode is maintained off.
Figure 3.10: Buck-boost converter (a) circuit diagram (b) waveforms.
When the switch is turned off, the diode provides a path for the inductor current. Note the polarity of the diode which results in its current being drawn from the output. The buck–boost converter waveforms are depicted in Fig. 3.10b. The condition of a zero volt–second product for the inductor in steady state yields
Eq 3.16
Hence, the dc voltage transfer function of the buck–boost converter is
Eq 3.17
The output voltage VO is negative with respect to the ground. Its magnitude can be either greater or smaller (equal at D = 0.5) than the input voltage as the converter’s name implies. The value of the inductor that determines the boundary between the CCM and DCM is
Eq 3.18
The structure of the output part of the converter is similar to that of the boost converter (reversed polarities being the only difference). Thus, the value of the filter capacitor can be obtained from Eq. 3.15.
3.5.2 Flyback Converter
A PWM flyback converter is a very practical isolated version of the buck–boost converter. The circuit of the flyback converter is presented in Fig. 3.11a. The inductor of the buck–boost converter has been replaced by a flyback transformer. The input dc source VS and switch S are connected in series with the primary transformer. The diode D and the RC output circuit are connected in series with the secondary of the flyback transformer. Figure 3.11b shows the converter with a simple flyback transformer model. The model includes a magnetizing inductance Lm and an ideal transformer with a turns ratio n = N1/N2. The flyback transformer leakage inductances and losses are neglected in the model. It should be noted that leakage inductances, although not important from the principle of operation point of view, affect adversely switch and diode transitions. Snubbers are usually required in flyback converters. Refer to Fig. 3.11b for the converter operation. When the switch S is on, the current in the magnetizing inductance increases linearly. The diode D is off and there is no current in the ideal transformer windings. When the switch is turned off, the magnetizing inductance current is diverted into the ideal transformer, the diode turns on, and the transformed magnetizing inductance current is supplied to the RC load. The dc voltage transfer function of the flyback converter is
Eq 3.19
Figure 3.11: Flyback converter (a) circuit diagram (b) circuit with a transformer model showing the magnetising inductance Lm.
It differs from the buck–boost converter voltage transfer function by the turns ratio factor n. A positive sign has been obtained by an appropriate coupling of the transformer windings. Unlike in transformer buck-derived converters, the magnetizing inductance Lm of the flyback transformer is an important design parameter. The value of the magnetizing inductance that determines the boundary between the CCM and DCM is given by
Eq 3.20
The value of the filter capacitance can be calculated using Eq. (3.16).
3.6 C`uk Converter
The circuit of the C` uk converter is shown in Fig. 3.12a. It consists of dc input voltage source VS , input inductor L1, controllable switch S, energy transfer capacitor C1, diode D, filter inductor L2, filter capacitor C, and load resistance R.
Figure 3.12 Cuk converter (a) circuit diagram (b) waveforms.
An important advantage of this topology is a continuous current at both the input and the output of the converter. Disadvantages of the C`uk converter include a high number of reactive components and high current stresses on the switch, the diode, and the capacitor C1. Main waveforms in the converter are presented in Fig. 3.12b. When the switch is on, the diode is off and the capacitor C1 is discharged by the inductor L2 current. With the switch in the off state, the diode conducts currents of the inductors L1 and L2 whereas capacitor C1 is charged by the inductor L1 current. To obtain the dc voltage transfer function of the converter, we shall use the principle that the average current through a capacitor is zero for steady-state operation. Let us assume that inductors L1 and L2 are large enough that their ripple current can be neglected. Capacitor C1 is in steady state if
Eq 3.21
For a lossless converter
Eq 3.22
Combining these two equations, dc voltage transfer function of Cuk converter is
Eq 3.23
This voltage transfer function is the same as that for the buck–boost converter. The boundaries between the CCM and DCM are determined by
for L1 and for L2 Eq 3.24 & 25
The output part of the C` uk converter is similar to that of the buck converter. Hence, the expression for the filter capacitor C is
Eq 3.26
The peak-to-peak ripple voltage in the capacitor C1 can be estimated as
Eq 3.27
A transformer (isolated) version of the C` uk converter can be obtained by splitting capacitor C1 and inserting a high frequency transformer between the split capacitors.
Chapter 4
ZVS FLYBACK CONVERTER
4.1 Introduction
Among the conventional dc/dc converters, the flyback topology employs the fewest power components and devices. It is best suited for multiple output applications at total power levels below 150 W and dc line voltages above 100 V. However, as mentioned previously, the standard flyback is unable to meet the requirements for high power density and high efficiency. and the existing ZVS flyback converters have several previously mentioned drawbacks. Research for better solutions is hence required.
This chapter presents a ZVS flyback converter topology which is able to overcome some of the drawbacks of the existing topologies. The topology employs an auxiliary circuit that helps to achieve ZVS in the main switch, with addition of only few numbers of small power rating components and devices.
The converter operates in the discontinuous mode. The continuous mode operation is not recommended here since it is not easy to stabilize the converter. A steady state analysis of the converter is presented in this chapter to understand the behaviour and to develop performance characteristics.
The circuit description is made in Section 4.2. The modes of operation are detailed in Section 4.3. The steady state analysis is performed in Section 4.4 Performance is discussed in Section 4.5 and experimental verifications are made in Section 4.6.
4.2 Circuit Description
Fig. 4.1 shows a ZVS flyback converter topology employing an auxiliary circuit drawn inside the dashed line block. Outside the block is a standard flyback topology shown in Fig. 1.1.
Fig. 4.1: ZVS flyback converter topology.
In Fig. 4.1, Cin, is the input capacitor, T is the power transformer with windings Np (primary) and Ns (secondary), Lm the magnetizing inductance of Tr, Do is the output rectifier diode, Co is the output capacitor, Ro is the load and Q1 is the main switch.
The auxiliary circuit consists of (i) a snubber capacitor Csnb, which is connected in parallel with the main switch Q1, (ii) two coupled inductors Lap (primary) and Las. (secondary), (iii) two blocking diodes D1 and D2 and (iv) an auxiliary switch Q4.
4.3 MODES OF OPERATION
Fig. 4.2 shows key waveforms of the ZVS flyback converter. For each switching cycle, Ts, the converter operates in the following five intervals. In the operation of a standard flyback, there are no Intervals 1 and 3. These two intervals are fulfilled by the auxiliary circuit and are introduced here to achieve ZVS in the main switch, Q1, during both its turn-on and turn-off transients.
4.3.1 Interval 1 (t1< t < t)
Fig. 4.3(a) shows the circuit operation during this interval. At the beginning of this interval, 02 is turned ON. It has a zero current turn-on, because Lap is in series with it. Its drain-to-source voltage falls rapidly to zero, and a resonant loop consisting of Csnb, Lm and Lap, as shown in Fig. 4.4, is formed starts to discharge through Lap. The discharging current builds up a magnetic field in the core of the coupled inductors, transferring the stored energy in Csnb in the previous cycle to the core of Lap.
Fig. 4.2:Key waveforms of the converter of Fig. 4.1.
The converter operates in five modes per switching cycle. Variables are defined in Fig. 4.1
At the end of this interval, t = t1, Csnb is depleted. As a consequence, the drain of Q1 is pulled down to zero voltage, providing the ZVS condition for Q1 at its turn-on. During this interval, Co supplies the output current.
4.3.2 Interval 2 (t2 < t <t4)
Fig. 4.3 (b) shows the circuit operation during this interval. At the beginning of this interval, Q1 is turned ON under the zero voltage condition. Hence it has no turn-on losses. At the same moment, Q2 is turned OFF, stopping the current in Lap rapidly.
Fig. 4.3: Modes of operation of the converter of Fig. 4.1.
The rapidly falling current in Lap reverses the voltage polarity on the dotted ends of the coupled inductors. Thus D2 becomes forward biased and is forced to conduct.
When D2 is conducting, Las sees a constant voltage Vin. Through coupling, Lap sees a reflected voltage. This voltage is the stress voltage on Q4. By increasing the ratio of Las to Lap, the stress will be lower. This in turn reduces the turnoff switching losses in Q4. On the other hand, the current in Las, is decreasing linearly. In this way the stored energy in the core of the coupled inductors is gradually fed back into the input line. At t = ta, the process completes and D2 becomes reverse biased again.
Fig. 4.4: The equivalent circuit of the discharging resonant loop in Interval 1.
When Q1 is ON, the magnetizing inductor of Tr sees a constant voltage Vin. Thus, the current in Q1 rises linearly. In this way the energy is stored in the core of T in the same fashion as in a standard flyback converter. During this interval, Co supplies the output current.
4.3.3 Interval 3 (t3 < t ≤ t4)
Fig. 4.3 (c) shows the circuit operation during this interval. At the beginning of this interval, Q1 is turned OFF. Csnb is in the process of charging and it slows down the rise of the drain voltage of QI. A sufficient value of capacitance of Csnb will guarantee a ZVS turnoff. The current in the primary side is decreasing in a resonant mode, with an angular frequency determined by Lm and Csnb. The decreasing of the primary current reverses the polarity on the dotted ends of Tr. But before the voltage of the secondary side of Tr reaches the output voltage Vo, Do maintains reverse biased. Co supplies the output current during this interval.
4.3.4 Interval 4 (t4 < t ≤ t5)
Fig. 4.3(d) shows the circuit operation during this interval. At the beginning of this interval, the voltage of the secondary side reachesVo. Then Do is forward biased and begins to conduct. The secondary current refills Co, and also supplies the output current. In this way the stored energy in Tr is now transferred to the output.
The conduction of Do causes Ns to see a constant voltage Vo. This in turn clamps the voltages on both primary and secondary windings, and consequently, it clamps the voltage across the main switch Q1.
4.3.5 Interval 5 (t5 < t ≤ t1+Ts)
Fig. 4.3(e) shows the circuit operation during this interval. At the beginning of this interval, the stored energy in Tr is completely transferred to the load. Then Do is reversed biased again and Co supplies all the output current. The difference between the drain voltage of Q1 and the dc line voltage Vin causes a resonance in the network consisting of Lm and Csnb. At the end of Interval 5, a new cycle begins and intervals 1 through 5 repeat.
4.4 STEADY STATE ANALYSIS
The operating principle has been described in last section. In this section the steady state analysis is performed with the assumptions made below. In the analysis, the time varying variables such as the current and voltage of the principal components and devices are determined. Based on these variables, the performance of the converter is illustrated, and the resultant quantities such as the rms, average or peak current and voltage of the principal components and devices are obtained in Section 4.5.
In the analysis presented below, a closed form solution is obtained by solving a set of differential equations in each interval and by matching the boundary conditions at the boundary of each interval. The initial conditions are a function of the operating frequency fs the input dc line voltage Vin and the output power Po. These initial conditions can be obtained by the iterative process such as the Newton-Raphson method.
4.4.1 Assumptions, Definitions and Initial Conditions
For convenience, following assumptions are made:
(i) The steady state conditions have be established, and the converter is running at the nominal output voltage V and the static load condition: Po
(ii) Each component and device has ideal properties, that is
(1) Tr : the leakage inductance is ignored, and the core does not saturate,
(2) Lap, Las: the coupling factor is 1.0, and the core does not saturate,
(3) Ca, C snb: pure capacitors, and the capacitance of Co is infinitive,
(4) D1, D2, D0: the forward voltage drop is 0 V, the recovery time is 0 s,
(5) Q1, Q2: the on resistances are 0 ohm, the inherent capacitances are 0 F.
(iii) The magnetizing inductance of the transformer, L„„ is much larger than Lap.
Following parameters are defined:
ωn–angular fiequency of the resonant tank of Csub, and Lap
ω0 –angular frequency of the resonant tank of Csub, and Lap
iap–instantaneous current in Q2, I~P
Iap–peak current in Q2,
ias-instantaneous current in La-$,
Ias,–peak current in L,,
Impeak,,—peak magnetizing current in T,
iQ1–instantaneous current in QI,
is–instantaneous secondary current,
Is–peak secondary current.
n–reciprocal of tums ratio of Tr2, Ns/Np.
uQ1-instantaneous drain voltage of Q1 or voltage across Csnb
uQ2-4nstantaneous drain voltage of Q2,
V0–initial drain voltage of Q1 per switching cycle,
Vp-Q1–clampedv oltage stress of Q1 when it is OFF.
The analysis begins by stating the initial conditions of Interval 1:
(i) Q1 and Q2 are both OFF, and the drain voltage of the paralleled switches is Vo,
Eq 4.1
Eq 4.2
(ii) The magnetizing inductor L. and C,,,,, undergoes a resonance, but the resonant current in L°, is negligible,
Eq 4.3
(iii) Both D, and D. are reverse biased, and C,, supplies the total output current,
Eq 4.4
4.4.2 Interval 1 (t, < t ≤ t2}
This interval starts at t = t1, Q2 is turned on and Csnb and Lm forms a resonant tank as shown in Fig. 4.4. Hence the following equations govern the resonant process in this tank.
Eq 4.5
Eq 4.6
Eq 4.7
Combining Eqs. Eq 4.5 through Eq 4.7,
Eq 4.8
According to the assumption (iii), Lap<<Lm. Hence, Eq. Eq 4.8 can be approximated as,
Eq 4.9
By the definition made above,
Eq 4.10
Giving the initial conditions expressed in Eqs. Eq 4.1 through Eq 4.4, Eqs. Eq 4.9 and Eq 4.6 yield, respectively
Eq 4.11
Eq 4.12
Because D, and Do are reverse biased and OI is OFF and Q2 is ON, the following equations are found to govern the respective variables in this interval
Eq 4.13
Eq 4.14
At the end of this interval, the resonance completes a quarter of its period, i.e., w„ (t, – t1) equals ic/4. Thus, u.„ always reaches zero regardless of V. which is determined by f, TV„ and P
Eq 4.15
and ia,, reaches the peak value given by
Eq 4.16
The final value of each variable in Interval 1 defines the initial conditions of Interval 4.
4.4.3 Interval 2 (4 < t ≤ t3)
This interval starts at t = t2, Q2 is turned OFF and ia, falls immediately to zero. A current is forced to flow through La, and D2 and into the input dc line, with an initial current Io determined by the energy conservative equation, Eq 4.17)
Eq 4.17
which yields
Eq 4.18
Substituting Eq.Eq 4.16) into Eq 4.18),
Eq 4.19
Las sees a constant voltage Vin, As Q1 is ON, Lm also sees a constant voltage Vin. Thus,
Eq 4.20
Eq 4.21
As Q1 is ON and Q2 is OFF and Do is reverse biased, therefore
Eq 4.22
Eq 4.23
At t = ta, tas reaches zero. Thus, by letting ias be zero in Eqs. Eq 4.20) to can be found,
Eq 4.24
Hence the voltage stress on Q2 is governed by
Eq 4.25
At the end of this interval, t = t3, iQ1 reaches its peak value, as given by
Eq 4.26
where, fs is the switchuig frequency, and D is the switching duty cycle of Q1, which is required to regulate the output voltage at the static load conditions (discussed in Section 4.5.2) and is here equal to (t3-t2)/Ts.
The final value of each variable in Interval 2 defines the initial conditions of Interval 3.
4.4.4 Interval3 (t, < t ≤ t4)
This interval starts at t = t3, Q2 is tumed OFF and Csnb charged by im. Refering to Fig. 4.4, the drain voltage of Ql in this interval satisfies the following equation.
Eq 4.27
Giving the initial conditions determined by Eqs. Eq 4.21) and Eq 4.23). the solution of Eq. Eq 4.27) can be obtained as
Eq 4.28
where, by the definition made previously.
Eq 4.29
As both Q1 and Q2 are OFF and Do is reverse biased, other variables in this interval are found to be governed by the following equations, respectively,
Eq 4.30
Eq 4.31
Investigating the rising speed of uo, by differentiating Eq. Eq 4.28 and substituting Eq. Eq 4.29 into the result: Eq. Eq 4.31 reveals that the rising speed of ui„ is controlled by Csnb. Giving the proper value of Csnb will sufficiently slow down the rise of uQ1, and hence achieve ZVS in Q1 at the turn-off transient. The magnetizing current is given by
Eq 4.32
At the end of this interval, t = t,. it,,, reaches the clamped voltage as given by
Eq 4.33
Thus, the duration of this interval can be determined by substituting Eq. Eq 4.33 into Eq 4.28 and solving the resultant equation for (t3-t4). The final value of each variable in Interval 3 defines the initial conditions of Interval 4.
4.4.5 Interval 4 (t, < t <_ t5)
This interval starts at t = t,. D„ is forward biased and a current flows through N and Da into the output end. As Ns has a inductance equal to n2Lm, the initial value of the secondary current Isp can be obtained from the energy conservative equation,
Eq 4.34
which gives
Eq 4.35
N sees a constant voltage V , therefore
Eq 4.36
As Q1 and Q2 are OFF and uQ„ is clamped, thus, the following equations are obtained
Eq 4.37
Eq 4.38
Because the converter is operated in the discontinuous conduction mode, the secondary current i, will reach zero within one switching cycle. Thus, the relation between the peak value of the secondary current and the output power Pp is found to be
Eq 4.39
Hence, at the end of this interval, t = ts.
Eq 4.40
where, D'is the equivalent duty cycle of rectifier D,, and is equal to (t5-t4)fs.
The duration of this interval can be determined by combining Eqs. Eq 4.39 and Eq 4.40 and solving the resultant equation for D' The final value of each variable in Interval 4 defines the initial conditions of Interval 5.
4.4.6 Interval 5 (t5 < t s T+ t)
This interval starts at t = t5. Do is reverse biased again Q1 and Q2 are OFF. Csnb and Lm undergo a resonance and this resonance obeys Eq. Eq 4.27. Giving the initial conditions as determined by last interval, and solving the equation for uQ1,
Eq 4.41
Eq 4.42
As Do and D2 are reverse biased and Q1 and Q2 are OFF, thus,
Eq 4.43
At the end of this interval, t = Ts +t1, uQ1 reaches a voltage Vo, which is the steady state initial voltage of Interval 1 of each cycle. From Eq. Eq 4.41), it is found that
Eq 4.44
Since Lm is much larger than Lap by comparing Eqs Eq 4.42) to Eq 4.12), Iin is negligible and hence ignored in the analysis of Interval 1, that is.
Eq 4.45
The final value of each variable in Interval 5 defines the initial conditions of Interval 1 in the next switching cycle, which just repeats the same process as analyzed above.
4.5 PERFORMANCE
4.5.1 Effects of the Non-Ideal Components
The above analysis has been made under the assumptions of ideal components and devices. In fact, each component and device of the circuit has some non-ideal properties. For example leakage of transformer, the ON resistance and inherent capacitance of switches etc. It is important to determine whether they make a remarkable deviation.
It can be explained as follows. The ON resistance of switch causes the so called conduction losses. The inherent capacitors indeed have some effects on the performance of the switch. But the output capacitor of the switches can be combined with Csnb and the effects of input capacitor of the switches can be made negligible by employing strong gate drives. The blocking diodes in Fig. 4.1 can be chosen as nearly ideal ones, like the Schottky diode or the ultra-fast diode. However, the effect of the leakage inductances of the circuit is detectable on key waveforms.
The effects of the leakage inductance of the transformer become apparent in Interval 4. It is because in other intervals they can be combined with magnetizing inductance Lin, However, in Interval 4, the flux linked inductance (Lin) is clamped at a constant voltage (Vo/ n), but the leakage inductance is not affected by this clamp action. The leakage, called Lleak in the following discussion, undergoes a resonance governed by
Eq 4.46
where iQi ,rak is the voltage component of iin caused by the leakage, and
RFSR is the equivalent series resistance of the resonant loop.
The initial conditions of Eq 4.46 are given by Eq 4.21 and Eq 4.23. Thus, the solution of Eq 4.46 is
Eq 4.47
where,
Eq 4.48
Eq 4.49
Superimposing uQ1 ,uQk(t) onto uQ, will give the total voltage of Csnb.
Similarly, the leakage of Lap and the inherent drain-to-source capacitor of Q2 undergo another resonance between the turnoff of Q2 and ta, as given by
Eq 4.50
where La_leak is the leakage of Lan,
Cass Q2 is the inherent capacitance of Q2,