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Essay: Improving Connected Component Labeling Performance with Novel Algorithm and FPGA Execution

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  • Published: 1 April 2019*
  • Last Modified: 23 July 2024
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  • Words: 1,541 (approx)
  • Number of pages: 7 (approx)

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Evaluation of the features of vessels plays a significant part in various medical tests. For doing such assignments computations are required e.g., vessel width, color, reflectivity, tortuosity, unusual branching, or the happening of vessels of a definite width. If the number of vessels in an image is enormous, or by an enormous number of images is obtained, physical description of the vessels becomes hard or even impossible.[1]

Connected Component Labeling (CCL) is a fundamental characteristic of many computer vision systems. It permits the task of unique identifiers (labels) to different, disjoint connected components. Therefore it comprises an important phase in computerized surveillance or pattern recognition methods. [2]

Several computer image processing and computer vision approaches are being used in retinal image processing. Amid them, preliminary pre-processing methods tried on a retinal image, plays a vital role in improving the accuracy of image analysis and present processing steps. Connected component labeling is the most significant tool utilized in pre-processing stages in image analysis and in post processing stages.  After recognizing connected components of an image, each set of connected pels having same gray-level values are assigned the same unique region label. [3]

ALGORITHMS USED IN CONNECTED COMPONENT ANALYSIS

In this evaluation, they introduce a novel single-pass CCA algorithm, which removes the necessity for straight blanking periods in alreadymentioned techniques, and the FPGA execution of proposed algorithm which attains real-time handling for sequence of images.

The algorithm in as an acknowledged fast connected components labeling algorithm, is chosen for differentiating; and running time is the important estimation of the test. To have an additional particular reason, the best single pass algorithm that is planned for hardware execution is chosen also for comparison, and the resource usefulness and processing capacity are analyzed.

In this study, a real-time single-pass connected components analysis algorithm is suggested. differentiating with the existing single-pass CCA algorithms, the pel is positioned as a scan unit, the run is set as a labeling unit, and the association of labels in neighbouring rows are managed by the many-layer-index structure. On performing this, the equivalence can be determined as early as it is experienced, avoiding the need for waiting for the end of the row. Because of the desirable architecture, the algorithm can carry out single pass CCA on FPGA while the pixel is being conveyed. Researched outcome showed that the algorithm is fit for real-time management in the real-time automatic target recognition scheme. [4]

The two novel approaches in their paper proposed is utilized to largely improve the acceleration of connected component labeling algorithms. For alloting a label to a new object, most labeling algorithms use a scanning step that evaluates few of its neighbors. The main strategy exploits the weakness among the neighbors to reduce the number of neighbors studied. On reviewing eight connected components in a two dimensional image, it can minimize the number of neighbors studied from four to one in many cases. The next approach utilizes an array to store the equivalence information between the labels. It changes the pointer based rooted trees used to store the same equivalence information. It lessens the necessary memory and creates successive ending labels. Utilizing an array based in its place of the pointer based rooted trees accelerates the foresaid algorithms by a factor of 5 ∼ 100 in their tests on arbitrary binary images.

When the algorithms are assessed utilizing arbitrary digital images, it will be more interesting to see the performance on application data. It might be also interesting to provide better thorough analysis of the algorithms introduced. [5]

An advanced and common technique for connected-component labeling of images is presented. The algorithm introduced in their paper introduces images in prearranged order.  It means that the processing order depends only on the image description method and not on particular features of the image. The algorithm handles a wide different image description schemes. For adapting the standard UNION–FIND algorithm to allow reuse of non-permanent labels is revealed. It is done utilizing a method called age stabilising, in which, when two labels are mixed, the senior label will be the parent of the junior label. Their method can be assembled to exist together with the more traditional regulation of load balancing.  In it the label of larger heirs becomes the parent of the label with less heirs. Different image scanning sequences are checked and categorized. They also show that when the algorithm is distinctive to a pel array scanned in raster sequence, the whole processing time is sequential in the number of pels. The linear-time managing follows from an unconstraint property of the UNION–FIND algorithm, which maybe of unconstraint interest. This property expresses that under particular conditions on the input, UNION–FIND travels in time sequential in the numerical quantity of FIND and UNION actions. Under these restrictions, linear-time execution can be accomplished without replacing to the more intricate Gabow–Tarjan algorithm for disjoint set union. [6]

Their standard connected components labeling algorithm needs at least 2 passes from an image. Their paper presents an alteration of their algorithm that allows the resolution of merged labels to be postponed. This enables the ensuing data analysis step to be integrated with the labeling method, with the outcome of connected components will be examined in a single pass by collecting information on the region as they are made. It avoids the need for buffering the image, making the algorithm properly matched for organizing transmitting images over an FPGA (Field-Programmable Gate Array) or like embedded scheme having restricted memory. The FPGA-formed design shown could utilize 1 clock cycle per pixel with a little overhead to handle integrating of “U” shaped elements. It is shown that the worst case overhead is 20% of the image, although for standard images the overhead is less than 1%.

They are currently in the process of executing this plan on an FPGA, and thinking ways of optimising the prototype additionally to minimize the comparatively large necessities for the data and merger tables.[7]

Components neighbors-scan labeling algorithm for connected component labeling as a computational approach was presented in their study. The algorithm needed scanning from an image only once to label connected components. The algorithm initiated by scanning from the peak of the component’s group, prior to tracing all the components neighbors by utilizing the principal component’s data. There are preferable attributes in their algorithm because it is simple with advanced precision and less time spending. Utilizing a list of components, this method also gave other benefits as the data for the subsequent superior method.

Their technique was assessed with a group of binary images. In practically all cases, the method had effectively given the expected outcome. Normally, from the results the algorithm enhanced the acceleration approximately 67.4% through two times scanning technique. [8]

Their paper proposes a novel two-scan algorithm for labeling connected components in digital images. At the initial scan of their algorithm, every traditional two-scan labeling algorithm develops image lines one after other and develops pels one after other. On distinguishing, they develop image lines two by two and develop image pels two by two. By their algorithm, the average times for examining the neighbor pels for organizing a foreground pixel will reduce, that directs for an effective labeling processing. The outcomes of review on various kinds of images displayed that their method is more efficient than traditional label-equivalence-based labeling algorithms. There are many works remained for us to do in the future. For example, extending their method for labeling 3D binary images developing, an algorithm for parallel architectures, and implementing their algorithm by hardware [9]

Their approach calculates the connected components of a digital image in genuine time with no particular hardware support. In its place it uses the power and efficiency of the divide-and-conquer technique. This new method can calculate connectivity in a one thousand  seven hundred and sixty nine by one thousand one hundred sixty eight image in about 2, instead of  hundreds, of seconds. [10]

Their connected components algorithm uses a new method for similar mingling that carries out significantly partial revising through iterative steps, and finalizes with a total reliability upgrade at the last stage. The coding is done in SPLIT-C with the algorithms and run on different operating systems.

Their test results are consistent with the theoretical study and provide the best known implementation times for these two primitives, on contrasting with machine-specific executions.  [11]

In this paper they describe a two-scan labeling algorithm meanwhile, different from the traditional method, equivalences are ordered during the first pass in order to determine the accurate condition of equivalence classes at every time of the scan. It is achieved by combining classes as early as a novel equivalence is detected, the data structure utilized to help the combining being an easy 1D array. This technique permits the scrutiny for a discord to be conceded on class identifiers instead of on labels, it is necessary with the classical algorithm. They show that this significantly improves the effectiveness of the labeling process. The ideas of merging equivalence classes and performing inconsistent checks as class identifiers are present also in the algorithm by Samet et. al. However, this algorithm is further complicated comparing the previous one explained in their paper. Further the authors do not specify that executing conflict checks directly on equivalence classes improves the efficiency of the labeling process. [12]

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