Computer systems (CSS/FDC)
MCOMD1CSS
Sophie Lavis LAV15118101
s.lavis488@canterbury.ac.uk/sophie.lavis@hotmail.co.uk
CPU Design:
To create my diagram I used an online resource, (logic.ly/demo), this enabled me to gain a visual idea of how to lay out my logic gates.
Justification for design
I have chosen to layout my logic gates (Fig 1.) to show clearly the different elements that make up the CPU. I have chosen to use switches to indicate the binary input, for example if the switch is ‘on’ then it represents the binary number 1, if the switch is ‘off’ then it represents the binary number 0. I felt that this initial design was a good graphical way of visualising the processes and inputs.
I have chosen to use a button control signal, where by the user can decide what operation they wish the CPU to perform, either the ADD or AND function. Here I also used the visualisation method within my design to show the ‘button’ pressed down/connected to the circuit as 1 – AND function, and a raised/non connected button as 0 – ADD function.
Within the CPU design itself with the logic gates I have chosen to show them with clear pathways showing which functions interact and lead to the next function. I have chosen to use a mixture of AND, OR, XOR, and NOT gates to create my full adder with the AND function incorporated for the CPU to complete its operation as selected by the user.
I felt that to have a difference in colour use for the pathways within the CPU diagram would enable the different stages and operations to be identifiable.
To represent the outcomes of the input data and the operations performed within the CPU I have included the sum values (S1-4) within the truth tables (see appendix).
Flaws
The flaws within my CPU design is the layout. Despite being very visual it is very crowded. I feel that I should have created my diagrams smaller to enable less space to be taken up, therefore easier to read and trial run. I also feel that using flexible pathways rather than straight line pathways make the CPU design clustered and messy. If I were to re-design the CPU diagram and didn’t reduce the size or space taken up by the diagram then I would colour code each different function, the different levels of pathways.
I also feel that my diagram lacks complexity and looks too simple for the task it needs to complete. I feel that there should be more information included within the diagram to represent the brief. The CPU diagram could also be included within another diagram to show all the elements which affect it and integrate with the CPU, for example how the cache and RAM memory are different distances away from the CPU therefore affecting information recall time.
Efficiency
The average depth of my circuit is 4. This can be measured by the number of gates that the longest pathway passes through. The efficiency of the CPU can also be measured through the speed at which it takes to perform a task. The use of certain functions can also affect the speed. To measure the speed of my CPU we need to take into account the amount of functions the bit of information has to travel through, the type of movement – either serial or parallel and the type of memory used to store the information.
For example serial movement only allows bits of information to be sent one after another rather than all at one time, despite the remarkable cost the speed of the communication switches needs to be extremely fast to accommodate the information being sent chronologically, therefore if this switching time is not fast enough the process will end up very slow.
Another point to consider when calculating efficiency is the speed of the memory and memory recall of the information to be used within the operations needed. For example if we were to combine a small amount of fast memory which would cost more with a large amount of slow memory which would cost less, then it would equate to a similar speed at which the fastest register memory perform at. Therefore if I were able to mix some faster cache memory with some DRAM memory then I would save space per bit with the DRAM as it only requires one transistor and one capacitor per bit which enables the memory to be very dense .
Another contributing factor the efficiency of the CPU diagram relies upon the cost of the construction and running of the CPU. Therefore the more gates the CPU has the more costly it will be to create, my design with 24 gates. A logic gate costs 50p on average , when multiplied by 24 it would equate to £12 just for the logic gates within the CPU and not including wiring, casing, memory, control function, output functions. So it can get more costly with the more gates you have within your CPU.
Performance
Elements that effect the performance of the CPU includes cores, clock speed, and cache size and processor type. The CPU can house more than one processing section, each of these sections are referred to as cores, which contain an ALU, control unit and registers. For example a quad core processor within a computer. The clock rate is an indication of how fast the CPU runs, and shows how many instructions are dealt with within a second. The faster the CPU the more energy is produces and therefore gives off more heat which is not a good factor of performance. A CISC (complex instruction set computing) has a higher clock rate rather than RISC, therefore are more expensive to make are run.
Amendments and improvements
If I were to re-design the CPU diagram and didn’t reduce the size or space taken up by the diagram then I would colour code each different function, the different levels of pathways.
I would also re-design the CPU diagram so that it does not include as many gates therefore reduces costs or at least enables more money to be spend on increasing the speed of the CPU therefore improving the quality of the performance.
Future-proofing
To future proof my design I would reduce the gate numbers to reduce the percentage risk of failure and to reduce repair costs. The possibility of including more processors within the CPU will then enable it to still be able to keep up to speed and deal with instruction demands when hardware and software continue to improve and update in the future. Therefore if the amendments and improvements to the CPU design is implemented then the possibility of having more money for other things will also improve the possibility of better future proofing. This will also enable the speed to be increased in anticipation of a higher demand from the CPU within the same performance time frame.
Another method to future proof my CPU design would be to ensure that the downfalls of the current design are remedied and are not repeated, any form of prediction of issues with future needs from the CPU must be kept in mind and must enable the CPU to still function properly without any wastage such as energy, cost efficiency or space.
Ease of upgradeability
If I were tasked to add more operations (control signals) within current design I would ensure that during the initial compilation and creation of the CPU design I over ordered parts for this very purpose, to ensure that I do not have to spend more money in a separate scenario when the prices of gates or other hardware may have increased. I personally thing to physically upgrade the CPU design would not be as easy as I would initially think, yet if I were to re design the CPU diagram to enable future proofing then that would enable an easier yet not simplistic upgradability.
Appendix
And function truth table:
Input 1 Output Input 2 Output Input 3 Output Input 4 Output
A1 B1 F A2 B2 F A3 B3 F A4 B4 F
0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 1 0 0 1 0 0 1 0
1 0 0 1 0 0 1 0 0 1 0 0
1 1 1 1 1 1 1 1 1 1 1 1
Adder truth table:
Input A Input B Output
A1 A2 A3 A4 B1 B2 B3 B4 S1 S2 S3 S4 C
0 0 0 1 0 1 0 0 0 1 0 1 0
0 0 0 1 0 0 0 1 0 0 0 0 1
0 1 0 0 0 0 0 1 0 1 0 1 0
1 0 0 0 1 1 1 0 0 0 0 1 0
0 1 0 1 1 1 0 1 0 1 0 0 1
0 1 1 1 1 1 1 1 0 1 0 1 1
0 1 0 1 1 0 1 1 1 1 1 0 1
References
Type of resource Bibliography Example
Website simulator Logically Demo (2015)
Available from : http://logic.ly/demo/
[Accessed:3rd December 2015] Fig 1.
Academic learning resource Sahota, V.
(2015) “004_ComSys_Mem_ALU”
Pg. 6-9 Pg. 6 – “Each bit uses 1 transistor & 1 capacitor“
Website RS Online (2015)
Available from: http://uk.rs-online.com/web/c/semiconductors/standard-logic/standard-logic-gates/
[Accessed: 3rd December 2015] “..A logic gate costs 50p…”
Website CPU and memory (2015)
Available from: http://www.bbc.co.uk/education/guides/zmb9mp3/revision/3
[Accessed:3rd December 2015] “..The CPU includes cores…”