Due to the technology scaling and the power density, the size of transistors become smaller in order to support the high efficiency chips. With the increasing of the transistors, the voltage supply has been the most significant problem for designer because of each transistor need to get energy while executing. Thus, to avoid the overcapacity and overheat of chips, engineers need to take turn to execute each transistor which cause dark silicon era. In this paper, we provide some main challenges while executing the dark silicon areas and the solution, our goal is to help the designers for discovering the best performance of chips and lower down the power consumption.
I. Introduction
Nowadays, Embedded system has been applied in various field in the real world. However, in the process of design the chips, Dark silicon has become a significant challenge for both hardware and software designer. To improve the performance of the chip, designers embedded more and more transistors on it. Nevertheless, due to the thermal limits and power maximum, the waste of power and the over heat of chips began a challenge, the transistors won’t be able to turn on simultaneously. Thus, because of the power limit, power efficiency and the capacity of chip, some percentage of transistors need to be in a power down state in order to avoid the over load of the power efficiency and the thermal issue. The areas which lack of power supply are called dark silicon area. In order to improve the performance of chips, engineers start focusing on using dark silicon as a way for designer to reduce the power consumption, prevent the components and chip over heat which might cause the circuit short-cut. However, to find the best performance for dark silicon, engineers have been research for the multiple ways to solve the problems such as waste the energy for inaccurate circuit execution, transfer data from far location and the waste energy of general computing recently. [1]
II. Problems and solutions of the dark silicon in nowadays
As the introduction aforementioned, instead of power off some of transistors, engineers tend to use the dark silicon to improve the performance of chips. According to the relationship of energy efficiency and utilization of transistors, heterogeneous multicore chips is the popular way to design. While designing and applying the chips, there are several challenges that caused by the emergent of dark silicon which are (i) Circuit Re-designApplication, (ii) Utilization and Allocation (iii)Approximate Computing and (iv)Runtime management and Thermal issue. [7][8]
i. Circuit Redesigned
Due to the technology scaling, traditional circuit design will not be able to cool down in effective way. In order to get the minimize of the execution time and the best performance, designers need to redesign the circuit and there are several challenges which will be considered. First, synthesis of design space exploration is to determine the best performance by using optimal numbers of cores, also make sure each application will execute with stable and different Degree of Parallelism(DoP). Secondly, heterogeneous NoC for dark silicon is to propose an architecture called darkNoC which can specify each network layers for identify routers and variable power and frequency. Third, reliability challenge means that because of the reason that small transistors are impressionable to the Soft Error Rate(SER), so the percentage of SER in die area will increase, it can also be a significant effect for electro migration (energy might be waste for transfer data from far location). [2][3][7][9]
ii. Application utilization and allocation
Because of the consumption of the energy, the distribution and exploitation of application become a significant issue for dark silicon. The traditional applications usually have general purpose which means that they don’t have specific functionality, it increases the power waste and decrease the power efficiency. Nowadays, in order to fix the problem, designers decide to consider a particular functionality to each application such as on-chip accelerators, to approach the best configuration of energy efficiency and highly performance [6]. For instance, accelerator-rich CMP (ARC) is a framework application which can be efficiency allocate the accelerators and minimize the energy consumption[5]. Besides, the general-purpose applications have constraint exploitation, the poorly implementation areas will have low energy efficiency but high power consumption. Furthermore, the specific purpose of application executing will increase the dark silicon predictability. Thus, it is important for each application to have a specific purpose which can not only decrease the overhead used to lower the efficiency but also easy to share the data between each application [13].
iii. Approximate Computing
After evaluating the power density and the peak power limit, people found out that computing has been an important factor for exploiting dark silicon era. Considering the power limitation and the multicore scaling, approximate computing has been viewed as the most executable way to decrease the power waste and increase the efficiency. Furthermore, the approximate program will performed better also reduce the power consumption by using approximation-supporting processors [10]. In a recent paper [11], the authors proposed a general purpose of approximating computing based on three steps which are software disciplined programming, heterogeneous architecture design and approximate accelerators. The authors believe that to combined the approximating computing in programming phase, architecture phase and circuit phase, the performance of the chip will be better. To conclude, though approximating computing is not the only way for dark silicon era to get the best performance, it will be better that researchers can still focus on multiple ways in order to get the best configuration for the chips.
iv. Run Time and Thermal Management
Recently, the chips temperature has been effected by high power density and the buildup of heat. High temperature issue might cause some negative effect on the performance such as the accurate of data transfer computing and the efficiency of the chip. To maintain the lower temperature, run time or life time management is important. Nowadays, Thermal Design Power(TDP) has been used as a guideline to estimate the Maximum usage of chips. Due to the overheat, the chips won’t be able to perform normally and will cause the poor exploiting of the power supply. [4] In the recent study [12], for multicore system, the managing of runtime has been following by advanced runtime resource management (RRM) to allocate the power and manage application. The authors present an experiment which based on the purpose of decreasing the runtime, the experiment is about finding the best performance for the reliability model by using the reliability- aware power management while following Thermal safe power(TSF) or TDP guideline. Thus, by reducing the lifetime, temperature problem will be able to improve it and find the best performance.
III. Conclusion
In this paper, we have provided several challenges and solutions while executing the dark silicon era, by solving the problems which aforementioned, the transistors should be able to reduce the power consumption and find the best performance. Thus, the mainly focused for the designers should be redesigned the circuit, specify the different function for each processor, approximate computing on reliability module and decrease the runtime to avoid chips overheated. In the future, despite the technology scaling, people will still be able to find the high efficiency best performance for the chips and don’t need to worry about the thermal issue.