8.3 Introduction to the Pentium microprocessor
Pentium Architecture
The Pentium family of processors originated from the 80486 microprocessor. The term ''Pentium processor'' refers to a family of microprocessors that share a common architecture and instruction set. The first Pentium processors were introduced in 1993. It runs at a clock frequency of either 60 or 66 MHz and has 3.1 million transistors. Some of the features of Pentium architecture are
Complex Instruction Set Computer (CISC) architecture with Reduced Instruction Set Computer (RISC) performance.
Upward code compatibility.
64-Bit Bus
Multiple Instruction Issue (MII) capability.
Pentium processor uses Superscalar architecture and hence can issue multiple instructions per cycle.
The Pentium processor fetches the branch target instruction before it executes the branch instruction.
Pentium processor executes instructions in five stages. This staging or pipelining, allows the processor to overlap multiple instructions so that it takes less time to execute two instructions in a row.
When data is modified, only the data in the cache is changed. Memory data is changed only when the Pentium processor replaces the modified data in the cache with a different set of data.
The Pentium processor has two separate 8-kilobyte (KB) caches on chip, one for instructions and one for data. It allows the Pentium processor to fetch data and instructions from the cache simultaneously.
The Pentium processor has been optimized to run the critical instructions in fewer clock cycles than the 80486 processor.
Superscalar Architecture of Pentium
Operating modes
The Pentium processor has three operating modes such as:
Real-Address Mode
This mode provides the programming environment of the Intel 8086 processor, with a few extensions. Reset initialization places the processor in real mode where, with a single instruction, it can switch to protected mode.
Protected Mode
In this mode all instructions and architectural features are available, providing the highest performance and capability. This is the recommended mode that all new applications and operating systems should target.
System Management ModeThe Pentium microprocessor also provides support for System Management Mode (SMM). SMM is a standard architectural feature unique to all new Intel microprocessors, beginning with the Intel386 SL processor, which provides an operating-system and application independent and transparent mechanism to implement system power management and OEM differentiation features. SMM is entered through activation of an external interrupt pin (SMI#), which switches the CPU to a separate address space while saving the entire context of the CPU. SMM-specific code may then be executed transparently. The operation is reversed upon returning.
Pentium pipeline stages
The Pentium's basic integer pipeline is five stages long, with the stages broken down as follows:
Pre-fetch/Fetch
Instructions are fetched from the instruction cache and aligned in pre-fetch buffers for decoding.
Decode1
Instructions are decoded into the Pentium's internal instruction format. Branch prediction also takes place at this stage.
Decode2
Same as above and microcode ROM kicks in here, if necessary. Also, address computations take place at this stage.
Execute
The integer hardware executes the instruction.
Write-back
The results of the computation are written back to the register file.
Pentium pipeline stages
Floating Point Unit
There are 8 general-purpose 80-bit Floating point registers. Floating point unit has 8 stages of pipelining. First five are similar to integer unit. Since the possibility of error is more in Floating Point unit (FPU) than in integer unit, additional error checking stage is there in FPU.
Floating Point Unit
FDD – Floating Point Division
FRD – Floating Point Rounding
FEXP – Floating Point Exponent
FADD – Floating Point Addition
FMUL – Floating Point Multiply
FAND – Floating Point And
Difference between 80486 and Pentium processor
Table below summarizes the fundamental differences between the basic features of 486 and Pentium families. Microprocessors have served largely separate markets and purposes: business PCs and engineering workstations. The PCs have used Microsoft's DOS and Windows operating systems whereas the workstations have used various features of UNIX.
The PCs have not been utilized in the workstation market because of their relatively modest performance, especially with regard to complicated graphics display and floating-point calculations. Workstations have been kept out of the PC market partially because of their high prices and hard-to-use system software.
The Pentium has brought the PCs up to workstation-class computational performance with sophisticated graphics. The Intel Pentium is a 32-bit microprocessor with a 64-bit data bus. The Intel Pentium, like its predecessor the Intel 80486, is 100% object code compatible with 8086/80386 systems. BICMOStechnology is used for the Pentium.
The Pentium processor has three modes of operation which determines which instructions and architecture features are accessible. In real-address mode, the Pentium processor runs programs written for 8086 or for the real-address mode of an 80386 or 80486.
The architecture of the Pentium processor in this mode is identical to that of the 8086 microprocessor. In protected mode, all instruction and architectural features of the Pentium are available to the programmer. Some of the architectural features of the Pentium processor include memory management, protection, multitasking and multiprocessing. While in protected mode, the virtual 8086 (v86) mode can be enabled for any task. For the v86 mode, the Pentium can directly execute "real-address-mode" 8086 software in a protected, multitasking environment.
The Pentium processor is also provided with a system management mode(SMM) similar to the one used in the 80486SL, which allows to design for low power usage. SMM is entered through activation of an external interrupt pin (system management interrupt, SMI#). In December 1994, Intel detected a flaw in the Pentium chip while performing certain division calculations. The Pentium is not the first chip that Intel has had problems with. The first version of the Intel 80386 had a math flaw that Intel quickly fixed before there were any complaints. Some experts feel that Intel should have acknowledged the math problem in the Pentium when it was first discovered and then have offered to replace the chips. In that case, the problem with the Pentium most likely would have been ignored by the users. However, Intel was heavily criticized by computer magazines when the division flaw in the Pentium chip was first detected.
The flaw in the division algorithm in the Pentium was caused by a problem with a look-up table used in the division. Errors occur in the fourth through the fifteenth significant decimal digits. This means that in a result such as 5.78346, the last three digits could be incorrect. For example, the correct answer for the operation 4,195,835 – (4,195,835 + 3,145,727) + (3,145,727) is zero. The Pentium provided a wrong answer of 256. IBM claimed this problem can occur once every 24 days. Intel eventually fixed the division flaw problem in the Pentium.
The Pentium microprocessor is based on a superscalar design. This means that the processor includes dual pipelining and executes more than one instruction per clock cycle; note that scalar microprocessors such as the 80486 family have only one pipeline and execute one instruction per clock cycle and superscalar processors allow more than one instruction to be executed per clock cycle.
The Pentium microprocessor contains the complete 80486 instruction set along with some new ones. Pentium's on-chip memory management unit is completely compatible with that of the 80486.
The Pentium includes faster floating-point on-chip hardware than the 80486.
Pentium's on-chip floating-point hardware has been completely redesigned over the 80486. Faster algorithms provide up to ten times speed-up for common operations such as add, multiply and load. The two instruction pipelines and on-chip floating-point unit are capable of independent operations. Each pipeline issues frequently used instructions in a single clock cycle. The dual pipelines can jointly issue two integer instructions in one clock cycle or one floating-point instruction in one clock cycle.
Branch prediction is implemented in the Pentium by using two prefetch buffers, one to prefetch code in a linear fashion and one to prefetch code according to the contents of the branch target buffer (BTB), so the required code is almost always prefetched before it is needed for execution. Note that the branch addresses are stored in the branch target buffer (BTB).
There are two instruction pipelines, the U pipe and the V pipe, which are not equivalent and interchangeable. The U pipe can execute all integer and floating-point instructions, whereas the V pipe can only execute simple integer instructions and the floating-point exchange register contents (FXCH) instructions.
The instruction decode unit decodes the prefetched instructions so that the Pentium can execute them. The control ROM includes the microcode for the Pentium processor and has direct control over both pipelines. A barrel shifter is included in the chip for fast shift operations.
Advanced Features
The Pentium P54C processor is the product of a marriage between the Pentium processor's architecture and Intel's 0.6-micron, 3.3-V BiCMOS process The Pentium processor achieves higher performance than the fastest Intel486 processor by making use of the following advanced technologies.
Pipeline Architecture:
Like the Intel486 processor, the Pentium processor executes instructions in five stages. This staging or pipelining, allows the processor to overlap multiple instructions so that it takes less time to execute two instructions in a row. Because of its superscalar architecture, the Pentium processor has two independent processor pipelines.
Superscalar Execution:
The Intel486 processor can execute only one instruction at a time. With superscalar execution, the Pentium processor can sometimes execute two instructions simultaneously.
Dual 8-KB On-Chip Caches:
The Pentium processor has two separate 8-kilobyte (KB) caches on chip–one for instructions and one for data–which allows the Pentium processor to fetch data and instructions from the cache simultaneously.
Branch Target Buffer:
The Pentium processor fetches the branch target instruction before it executes the branch instruction.
64-Bit Bus:
With its 64-bit-wide external data bus (in contrast to the Intel486 processor's 32-bit- wide external bus) the Pentium processor can handle up to twice the data load of the Intel486 processor at the same clock frequency.
Write-Back Cache:
When data is modified; only the data in the cache is changed. Memory data is changed only when the Pentium processor replaces the modified data in the cache with a different set of data
Floating-Point Optimization:
The Pentium processor executes individual instructions faster through execution pipelining, which allows multiple floating-point instructions to be executed at the same time.
Instruction Optimization:
The Pentium processor has been optimized to run critical instructions in fewer clock cycles than the Intel486 processor.
Pentium Extensions:
The Pentium processor has fewer instruction set extensions than the Intel486 processors. The Pentium processor also has a set of extensions for multiprocessor (MP) operation. This makes a computer with multiple Pentium processors possible.
A Pentium system, with its wide, fast buses, advanced write-back cache/memory subsystem and powerful processor, will deliver more power for today's software applications and also optimize the performance of advanced 32-bit operating systems and 32-bit software applications.